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1 of 172 march 19, 2007 ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri t ten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. device overview the idt80KSBR200 is a high speed serial buffer (serb) that can connect to any serial rapidio compliant interface. this device is built to work with any srio device and especially with the idt pre-processing switch (pps), idt70k200. the serb performs buffering and off-loading of data as well as buffer-delay of data samples in various environments. this device primarily acts as an master in which the serb bursts data to a programmed memory location once some criteria have been meet. this combination of storage and flexibility make it the perfect buffering solution for srio systems. features serial rapidio port interface - srio ? one four-lane (4x) link, configurable to one-lane (1x) link ? port speeds selectable: 3.125 gbps, 2.5 gbps, or 1.25 gbps ? short haul or long haul reach for each phy speed ? support 8-bit and 16-bit deviceid ? error management supports standard ? srio version 1.3 ? class 1+ end point device 10 gbps throughput 18mbit internal density programmable target address packet tally indicator packet interval timer replace missing packet optional external qdr sram available ? up to 72mbit external qdr sram ? qdr sram, 200 mhz; (18m, 36m, 72m) seamless integration of inte rnal and external memory ? internal and external memory functions as a single buffer single port buffering status flags for combined internal/external memories ? full, empty, partially empty, partially full direct or polled operation of flag status bus optional watermark ? serial buffer can either send a flag or transmit data at a specific packet count interface - i 2 c interface port ? one i 2 c port for maintenance and error reporting interface - jtag interface ? jtag functionality for boundary scan and programming high-speed cmos technology ? 1.2v core operation with 3.3/2.5v jtag interface package: 484-pin plastic ball grid array ? 23mm x 23mm, 1.0mm ball pitch advanced datasheet 80KSBR200 srio serial buffer flow-control device tck tms tdi tdo j t a g i n p u t d e s e r i a l i z e r o u t p u t s e r i a l i z e r 1 x/4x srio i nterface s - p o r t 1 c o m m a n d i n t e r p r e t e r 3 2 + 4 b i t p a r a l l e l 3 2 + 4 b i t p a r a l l e l cq c q k/k a q d s-port 1 p-port hardwire config 2 2 rd wr qdr c lk 2 fr phy c lk flags f l a g b u s 2 8 i n t e r r u p t f l a g c l k f l a g r e q u e s t m u x 3 mr scl sda i 2 c configuration and flag registers drw01 dsc-6730 m u x 1 0 queue 0 18 mbits block diagram
2 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes
3 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes table of contents 1.0 functional description 9 interface overview 10 2.0 applications 13 pps data storage 13 compatible external memory 13 3.0 protocols 15 serb packet characteristics 15 srio specification 15 srio simplified overview 17 the srio packet 18 the srio control symbols 24 use of crc and crc errors 24 parallel port interface 24 4.0 data handling 25 inputting data to the queues 25 outputting data from the queues 25 use of acknowledgements 26 idles 27 case scenarios 27 water levels and watermarks 28 missing packet detection and replacement 29 packet tally indicator 31 packet interval timer 31 protocol translation 31 5.0 doorbells and interrupts 33 doorbell characteristics 33 external interrupt pins 34 6.0 device programming 35 vendor ids 35 memory map 35 programming and reset 37 7.0 error management 41 srio errors and error handling 41 system software error notification 41 srio errors supported 42 other serb errors 61 8.0 registers 63 srio registers 63 configuration registers 88 serb error counter registers 100 serdes quad control registers 102 flag and flag mask registers 102 9.0 reset and initialization 111 speed select 111 srio reset control symbol 111 jtag reset 111 system initialization 111 initialization of rio ports 112 10.0 reference clock 113 reference clock electrical specifications 113 11.0 absolute maximum ratings 114
4 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes recommended temperature and operating voltage 115 ac test conditions 115 12.0 i 2 c-bus 117 i 2 c device address 117 signaling 117 figures 118 i 2 c dc electrical specifications 119 i 2 c ac electrical specifications 120 i 2 c timing waveforms 121 13.0 serial rapidio tm ac specifications 123 overview 123 signal definitions 123 equalization 124 explanatory note on xmt and rcv specifications 124 transmitter specifications 124 receiver specifications 127 14.0 parallel port electrical characteristics 131 ac electrical characteristics 131 15.0 jtag interface 135 ieee 1149.1 (jtag) & ieee 1149.6 (ac extest) compliance 135 system logic tap controller overview 135 signal definitions 135 test data register (dr) 136 instruction register (ir) 139 usage considerations 141 jtag configuration register access 142 jtag dc electrical specifications 143 jtag ac electrical specifications 144 jtag timing specifications 144 16.0 pinout & pin listing 145 pinout 145 pin listing 146 17.0 package specifications 169 package physical & therm al specifications 169 package drawings 170 18.0 references & standards 172 19.0 revision history 172 advanced datasheet: definition 172 20.0 ordering information 172
5 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes list of tables table 1: serb memory map 35 table 2: port-write packet data payload for error reporting 42 table 3: physical rio errors detected 42 table 4: physical rio threshold response 44 table 5: hardware errors for nread transaction 45 table 6: hardware errors for maintena nce read/write request transaction 47 table 7: hardware errors for rio write class transactions 51 table 8: hardware errors for swrite class transactions 53 table 9: hardware errors for maintenance response transactions 54 table 10: hardware errors for response transactions 57 table 11: hardware errors for reserved ftype 60 table 12: rio base feature address space 64 table 13: device id car 64 table 14: device information car 65 table 15: assembly id car 65 table 16: assembly info car 65 table 17: process element features car 66 table 18: source operations car 67 table 19: destination operations car 67 table 20: processing element logical layer control csr 68 table 21: local configuration space base address 1 csr 69 table 22: base device id csr 69 table 23: host base device id lock csr 70 table 24: component tag csr 70 table 25: rio extended features address space 71 table 26: 1x/4x lp-serial register block header 72 table 27: port link time-out csr 72 table 28: port response time-out csr 72 table 29: port general control csr 73 table 30: port 0 link maintenance request csr 73 table 31: port 0 link maintenance response csr 74 table 32: port 0 local ackid status csr 74 table 33: port 0 error and status csr 75 table 34: port 0 control csr 77 table 35: error management extensions block header 78 table 36: logical/transport layer error detect csr 78 table 37: logical/transport layer error enable csr 79 table 38: logical/transport layer address capture csr 81 table 39: logical/transport layer device id capture csr 81 table 40: logical/transport layer control capture csr 82 table 41: port-write target device id csr 82 table 42: port 0 error detect csr 83 table 43: port 0 error rate enable csr 83 table 44: port 0 attribute capture csr 85 table 45: port 0 packet/control symbol capture 0 csr 85 table 46: port 0 packet/control symbol capture 1 csr 86 table 47: port 0 packet/control symbol capture 2 csr 86 table 48: port 0 packet/control symbol capture 3 csr 86 table 49: port 0 error rate csr 87 table 50: port 0 error rate threshold csr 88 table 51: reset and command register 89 table 52: serial port configuration register 90 table 53: parallel port configuration register 90 table 54: memory allocation register 90
6 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes table 55: lost packet replacement register 91 table 56: source and destination id register 91 table 57: pae / paf register 92 table 58: watermark register 92 table 59: waterlevel register 92 table 60: space available register 92 table 61: mbist control register 93 table 62: qbist control register 93 table 63: jtag device id register 94 table 64: case scenario packet header register 95 table 65: case scenario start address register 95 table 66: case scenario next address register 96 table 67: case scenario stop address register 96 table 68: case scenario frame register 97 table 69: missing packet start address register 97 table 70: missing packet current address register 98 table 71: missing packet address increment register 98 table 72: missing packet stop address register 98 table 73: data packet interval timer register 99 table 74: doorbell packet interval timer register 99 table 75: missing packet size register 99 table 76: missing packet address logging register 99 table 77: missing packet address logging register for ti dsp 100 table 78: s-port data packet received counter 100 table 79: s-port data packet transmitted counter 100 table 80: s-port priority packet received counter 101 table 81: s-port priority packet transmitted counter 101 table 82: s-port packet received counter 101 table 83: s-port packet transmitted counter 102 table 84: serdes quad control register 102 table 85: flag and flag mask register 103 table 86: s-port link status register 104 table 87: device configuration error register 104 table 88: srio dma status register 105 table 89: missing packet flag register 106 table 90: fifo queue empty flag register 106 table 91: fifo queue full flag register 107 table 92: dsp interrupt flag register 108 table 93: tally doorbell flag register 109 table 94: missing packet programmable flag register 109 table 95: port speed selection pin values 111 table 96: input reference clock jitter specification 113 table 97: absolute maximum ratings 114 table 98: recommended temperature and operating voltage 115 table 99: ac test conditions (vdd3 = 3.3v / 2.5v); jtag, i2c, rst 115 table 100: typical power figures 116 table 101: i2c static address selection pin configuration 117 table 102: p-port ac electrical characteristics 132 table 103: jtag pin description 135 table 104: instructions supported by 80KSBR200?s jtag boundary scan 139 table 105: system controller device id register 140 table 106: system controller d evice id instruction format 141 table 107: data stream for jtag configuration register access mode 142 table 108: pin listings 146
7 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes list of figures figure 1: diagram of serb interfaces 10 figure 2: pps data storage 13 figure 3: generic srio request packet 18 figure 4: srio physical layer header 19 figure 5: transaction types (8 or 16) 19 figure 6: transaction id range for srio packet generating entities 22 figure 7: srio maintenance request packet (type 8) 23 figure 8: srio maintenance response packet (type 8) 23 figure 9: typical srio packet showing lo cation of source and destination ids 27 figure 10: srio doorbell packet 33 figure 11: reset timeline 111 figure 12: ref_clk representative circuit 113 figure 13: ac output test load (jtag) 115 figure 14: ac output test load (i2c) 116 figure 15: srio lanes test load 116 figure 16: write protocol with 10-bit slave address (ads = 1) 118 figure 17: read protocol with 10-bit slave address (ads = 1) 118 figure 18: write protocol with 7-bit slave address (ads = 0) 119 figure 19: read protocol with 7-bit slave address (ads = 0) 119 figure 20: i2c sda & scl dc electrical specifications (vdd3 = 3.3v) 119 figure 21: i2c sda & scl dc electrical specifications (vdd3 = 2.5v) 120 figure 22: specification of the sda & scl bus lines for f/s-mode i2c-bus device 120 figure 23: i2c timing waveform 121 figure 24: differential peak-peak voltage of transmitter or receiver 123 figure 25: short run transmitter ac timing specifications - 1.25 gbaud 124 figure 26: short run transmitter ac timing specifications - 2.5 gbaud 125 figure 27: short run transmitter ac timing specifications - 3.125 gbaud 125 figure 28: long run transmitter ac timing specifications - 1.25 gbaud 125 figure 29: long run transmitter ac timing specifications - 2.5 gbaud 126 figure 30: long run transmitter ac timing specifications - 3.125 gbaud 126 figure 31: transmitter output compliance mask 127 figure 32: transmitter differential output eye diagram parameters 127 figure 33: receiver ac timing specifications - 1.25 gbaud 128 figure 34: receiver ac timing specifications - 2.5 gbaud 128 figure 35: receiver ac timing specifications - 3.125 gbaud 129 figure 36: single frequency sinusodial jitter limits 129 figure 37: receiver input compliance mask 130 figure 38: receiver input compliance mask parameters exclusive of sinusodial jitter 130 figure 39: p-port signals connected to a qdrii sram 131 figure 40: timing waveform of combined read and write cycles 133 figure 41: diagram of the jtag logic 135 figure 42: state diagram of the 80KSBR200?s tap controller 136 figure 43: diagram of observe-only input cell 137 figure 44: diagram of output cell 137 figure 45: diagram of output enable cell 138 figure 46: diagram of bi-directional cell 138 figure 47: implementation of write during configuration register access 142 figure 48: implementation of read during configuration register access 143 figure 49: jtag dc electrical specifications (vdd3 = 3.3v) 143 figure 50: jtag dc electrical specifications (vdd3 = 2.5v) 143 figure 51: jtag ac electrical specifications 144 figure 52: jtag timing specifications 144
8 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes figure 53: 80KSBR200 pinout 145 figure 54: serb package drawing (1 of 2) 170 figure 54: serb package drawing (2 of 2) 170
9 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes 1.0 functional description the idt80KSBR200 is a serial rapidio tm sequential buffer (serb) flow-control device consisting of up to 18mbits of on-chip memory with expansion of one qdr sram externally bringing the total buffering capacity to 90mbits of storage. this device is built to work with any srio device and especially with the idt pre-processing switch (pps) number idt70k200. in this configuration, the main application is working in conjunction with the pps. in applications were multiple dpss are used with the pps, the serb can function as an over-flow port to handle traffic that is block on any given port or, as a delay buffer to store data and present it at a later time. this is important in dps applications were time samples are compared with the previous sample such as cellular base stations. please refer to the application note ?serial buffer and pre-processing switch?. the serb fully complies to the srio specification version 1.3 and is implemented to a class 1+ end-point device. this device operates as a master. in the srio environment, a master is defined as a device that originates data trans- fers, either to or from that device. a slave is one that re sponds to commands from other devices to move data. as a master, the serb can receive data and at a pre-programmed water level (number of packets), the device will form and transmit either packets or status (e.g., doorbells) to a programmed location. the serb performs buffering and off-loading of data as well as buffer-delay of data samples in various environments. this device can act as a master in which the serb writes data to a programmed location once the criteria have been meet. this combination of storage and flexibility make it the perfect buffering solution for srio systems. for applications requiring larger buffers , an additional 72mbits of qdr sram can be attached via the parallel port. the two memories are seamlessly connected by the serial buffer to form a large, 90 mbit buffer memory. the qdr sram interface runs at speeds of only 156.25mhz allowing lower cost memories to be used as well as easier board layout. data rates still support up to 10gbits/s (oc-192) thoughput in the device to maintain full srio four-lane compliance. the device provides full flag and empty flag status for t he queue for write and read operations respectively. also a programmable almost full and almost empty flag for the queue is provided. a jtag test port is provided running at 3.3v, device has a fully functional boundary scan feature, compliant with ieee 1149.1 standard test access port and boundary scan architecture. the serb can also be programmed via the jtag port. there is also an i 2 c processor port for programming and retrieving information from the configuration registers. the device is configured into a single queue comprising the fu ll internal memory and potentially the external memory if attached. the device treats the full amount of memory, wether internal or a combination of internal and external, as a single memory block. status flags from that queue, either referr ing to the writes (full flags) or the reads (empty flags) to or from that queue represent the total amount of memory. fl ags can be read from the serial port or from the i 2 c or jtag port. proactive flags can be configured to send a doorbell and/or c hange the interrupt pin once a flag is set. partial full and empty flags can be programmed to provide reaction time for wr ites and reads respectively. flags associated with reaching water marks are available in addition to the full and empty flags. further information regarding this device and follow-on devices with added functionality are available from idt.
10 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes 1.1 interface overview figure 1 diagram of serb interfaces 1.1.1 srio port the srio interface is the main communication port on the chip. this port is compliant with the serial rapidio tm v. 1.3 specifications. please refer to the serial rapidio tm specifications for full detail. there are 4 uni-directional differential links for a total of 8 pins. each can run at 1.25, 2.5, or 3.125gbps programmable. both srio data (sample) and maintenance packets are transmitted and received on these links. 1.1.2 parallel port p-port interface is used as a memory expansion port. as a memory expansion port, one of the designated qdr sram devices can be connected. if p-port is connected to one of t he designated sram devices, it will maintain the clocking and full interconnection to drive the sram device. 1.1.3 i 2 c bus this interface may be used as an alternative to the standard srio or jtag ports to program the chip and to check the status of registers - including the error reporting registers. it is fully compliant with the i 2 c specification, it has 13 pins and supports both fast- and slow-mode buses [1]. refer to the ?i 2 c? chapter for full detail. 1.1.4 jtag tap port this tap interface is ieee1149.1 (jtag) and 1149.6 (ac extest) compliant [10, 11]. it may also be used as an alterna- tive to the standard srio or i 2 c ports to program the chip and to check the st atus of registers - including the error reporting registers. it has 5 pins. refer to the jtag chapter for full detail. idt80KSBR200 serial buffer (serb) . . . . . . srio 4 tx lanes 1.25, 2.5 or 3.125gbps srio 4 rx lanes 1.25, 2.5 or 3.125gbps jtag interface (5 pins) i 2 c interface 400khz f/s (13-pins) r_ext (external resistance ) master reset ref_clock (2 pins) irq output (2 pins) p-port clock (4-pins) p-port rd/wr ctrl . . . p-port address (23 pins) p-port d bus (36 pins) p-port q bus (36 pins)
11 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes 1.1.5 interrupt (irq ) an interrupt output is provided in support of error managem ent functionality. this output may be used to flag a host processor in the event of error conditions within the dev ice. refer to the error management section for full detail. 1.1.6 reset a single reset pin is used for full reset of the serb, incl uding setting all registers to power-up defaults. refer to the reset & initialization section for full detail. 1.1.7 clock the single system clock (ref_clk+ / -) is a 156.25 mhz differential clock input. refer to the clock section for full detail. 1.1.8 r-ext (rextn & rextp) these pins are used to establish the drive bias on the serdes output. an external bias resistor is required. the two pins must be connected to one another with a 12k ohm resistor. this provides cml driver stability across process and temperature. 1.1.9 spd[1:0] speed select pins. these pins define the srio port speed at reset. the reset setting may be overridden by subse- quent programming of the serial port c onfiguration register. spd[1:0] = {00 = 1.25g, 01 = 2.5g, 10 = 3.125g, 11 = reserved}. these pins must remain statically biased after power-up.
12 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes
13 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes 2.0 application 2.1 pps data storage the serb?s primary application is for a basestations using the idt?s pre-processing switch (pps). the serb will be a storage device, holding large amounts of data passed to it by the pps and with all of its internal memory allocated to queue 0. in this application, the s-port on the serb will connect to one of the 4x ports of the pps. the pps will pass approximately 10ms of data to the serb at which time the serb will start to pass it back to the pps as a multicast. it is expected that the data flow will remain constant with 10m s (or other designated quantity) worth of data always in storage. the basestation uses the data for decryption purposes. the following are items of note concerning the pps application: the serb has the ability to act as a simple master. ? the serb's application with the pps will be to broadcast data. it must be a master to perform a broadcast, even if the data is requested. ? the serb has the ability to initiate writes. mainly to prevent overflow and to perform broadcasts when waterlevel is reached (timed event). this avoids requiring the dsp to increase congestion by requesting data and controlling the serb. the serb will typically perform swrites. ? the target address(s) generated by the serb is programmable. ? the packets are stored in the format they come in and are rebroadcast with simple changes to the headers the dsps have the ability to read the serb registers through the pps. ? the dsp may send a maintenance read/write packets to the serb requesting register information. figure 2 pps data storage 2.2 compatible external memories the p-port, as a fifo controller shall connect to an ex ternal memory device. t here are two designated memory devices, which may be connected to the serb. these are: qdrii-b4 sram with 36-bit bus in 36m size qdrii-b4 sram with 36-bit bus in 72m size only one memory may be connected to the p-port at a time. initial release of the serb will only support 72m density and support of other devices listed above to follow with subsequent release . expansion is available only through increased memory size. 2.2.1 memory default configurations: the memory default configuration on pow er up or hard reset is as follows: o u t p u t s e r i a l i z e r i n p u t s e r i a l i z e r c o m m a n d i n t e r p r e t e r c o m m a n d g e n e r a t o r data data e x t e r n a l m e m o r y i n t e r f a c e q d r i i m e m o r y c o n t r o l l e r high s peed serial lines high s peed serial lines cntl address queue 0 srio q d r 2 s r a m
14 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes no external memory is allocated, regardle ss of whether external memory is present. all sram is allocated to queue 0 p-port outputs default to valid states to prevent possible damage to external devices, unless p-port is physically disabled by the external pin.
15 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes 3.0 protocol the serb is a packet-handling device. the serb may be c onfigured to require all packets to be acknowledged, and hold all packets available for retransmission until acknowl edgement is received. incoming corrupted packets are dropped and issues a retransmission request. the negotiation for acknowledgement, retransmission and dropping packets is handled at the local interface level, without intervention of hi gher-level authorities. the serb does not forward any packet until it is fully received, verified, and acknowledged (if configured to verify). 3.1 serb packet characteristics 3.1.1 maximum packet size the srio specification requires a maximum packet size of 256 bytes plus overhead. the serb fully complies to this specification. 3.1.2 interface packet buffer size the srio specification has defined buffer sizes for the tr ansmit and receive buffers. included in the buffer specification is the requirement to transmit higher priority packets fi rst. upon transmission failure, and re transmission, the retransmis- sion may be held up and a higher priority packet interjected if one arrives. 3.1.3 multicast packets the serb has no special multicast capabilities. to perform a multicast, the case scenario should be set up to perform an swrite function. the destination id for the case scenar io should be set to a multicast address elsewhere in the system. the serb shall perform a multicast by sending the swrite to the user designated multicast address, along with the data. waterlevel multicast in the pps application is done the same way. when the waterlevel event is triggered, the serb issues an swrite multicast packet to the pps multicast address. the swrite command is generated by the case scenario. 3.2 srio specification the serb serial interface is a standard 1x/4x serial port with srio capabilities. in the pps application, the srio port act primarily as an srio end-point, but will work as a bus master to perform multicast operations. all the rio twg documents can be found on the rapidio members website: http://www.rapidio.org/apps/org/workgroup/twg/documents.php the following documents are the final version 1.2 spec ifications, which can be found under the members library section, version 1.3 of the specifications will replace these section files when they are approved by the steering committee: rapidio_spec.pdf part i through part iv of the spec., version 1.2 gsmlspec.pdf part v of the spec., version 1.2 serial.book.pdf part vi of the spec., version 1.2 inter-op.pdf part vii of the spec., version 1.2 errspec.pdf part viii of the spec., version 1.2 errata1.pdf errata 1 to version 1.2 of the spec. fcspec.pdf part ix of the spec., version 1.0 system_bringup_spec.pdf annex i of the spec. the version 1.3 files are currently: io_logical.pdf part 1: input/output logical specification msg_logical.pdf part 2: message passing logical specification cmn_trnspt.pdf part 3: common transport specification parallel_phy.pdf part 4: physical layer 8/16 lp-lvds specification
16 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes gsmlspec.pdf part 5: globally shared memory specification serial_book.pdf part 6: 1x/4x lp-serial physical layer specification inter-op.pdf part 7: system and device inter-operability spec errspec.pdf part 8: error management extensions specification fcspec.pdf part 9: flow control logical layer specification encapspec.pdf part 10: data streaming logical specification mcspec.pdf part 11: multicast extensions specification sbtg.pdf annex 1: software/system bring up specification there is a checklist for compliance to version 1.3 of the rio specification, which will be used to insure proper rio oper- ation. 3.2.1 rapidio spec. version 1.3 in compliance with the srio specification, the port has the ability to connect directly to a 1x/4x srio port on the pps device, or connect to any other srio compliant 1x/4x port. th is includes the standard lane fail functions where a failure of any lane on a 4x port will force the device into a 1x operation on lane 0 or lane 2. the serb has no requirement to perform with more than a single 1x port. restated, s-port shall be either a 4x port or a 1x port as designated by the configuration or fail mode, but shall never be four 1x ports operating simultaneously. the rio specification is a universal specification and all sect ions do not fully apply to the serb. each of the parts of the specification will be listed individually below along with the co mpliance level for the serb. some of the documents are not complete and published. some are working group showings. each chapter is discussed in a separate section below. part 1: input/output logical specification the serb device shall abide by this spec. part 2: message passing logical specification the serb device shall abide by this spec. part 3: common transport specification the serb device shall abide by this spec. part 4: physical layer 8/16 lp-lvds specification the serb device does not support this spec. part 5: globally shared memory logical specification the serb device does not support this spec. part 6: physical layer 1x/4x lp-serial specification the serb shall abide by this spec. part 7: system and device inter-operability specification the serb device shall comply with the generic class requirements (class 1+). part 8: error management extensions specification the serb device shall comply with this spec. part 9: flow control logical layer specification the serb devices does not support this spec. part 10: data streaming logical specification the pps device does not support this spec. part 11: multicast extensions specification serb device shall abide by this spec (do nothing). a multicast for serb is a simple write to an address.
17 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes annex i: software/system bring up specification already comply. approved showings the following documents are approved showings in the twg. each of them will be discussed in detail. 04-11-00031.001 change to the spec of the serial rapidio receiver sinusoidal jitter tolerance mask. idt serdes is tuned to this spec. 3.2.2 summation of rio registers the serb shall include all registers required by the rio spec for configuration. 3.2.3 srio priorities srio has two forms of priority. the first is the standard srio priority. the second is the virtual channel form of srio. there is a bit set in the data stream where vc = 0 designat es standard srio priorities, while vc = 1 designates virtual channels. the serb shall not use virtual channels, but pass any vi rtual channel data as if it were sent with standard priority. standard srio has four discrete levels of priority (two bits). added to the priority is the crf (critical request flow) bit which is a priority distinguishing bit within a priority (lsb), bringing the total number of priority bits to three. high prior ity packets are always sent before lower priority packets. low priority packets do not enter the data stream until the high priority packets are exhausted. the serb ignores the crf bit. in virtual channel prioritization, there are three bits that designate the virtual channel. these replace the srio two bit priority plus crf bit. with virtual c hannels, each channel is allocated a percentage of the total bandwidth. in this applica- tion, all channels are allocated some bandwidth regardless of t heir priority, preventing high priority packets from stealing the entire bandwidth. the serb shall not support virtual channel s, but instead will always transmit higher priority packets first. the srio user may transmit data on any priority with little regard to volume of data. for instance if there operating at close to full bandwidth with critical data, but would like to support additional service on an "as bandwidth available" basis, he may be running with most traffic on the higher priorities and limited capacity on low priorities. the response packet sent in most applications is intended to be sent at one priority level higher than the received packet, which would limit the usage of the top priority to re sponse packets, but it is not guaranteed that the user would not use the highest priority for other data. 3.3 srio simplified overview the operation of the srio bus is contained in the srio spec ification. the following comments are provided to provide a superficial understanding of the initialization of the interface, without researching the specifications. 3.3.1 srio sync the srio sync is accomplished by the transmitter sending continuous /k28.5/ codes (commas) on each lane until sync is accomplished. the state machine is shown on page vi-58 of the physical layer x1/x4 lp-serial specification for rapidio. the sync is tolerant of occasional /invalid/ code groups as shown in the state machine and will increase or decrease level of sync, based upon the error level of the inte rface. upon completion of sync, each serial lane should be able to successfully transmit and receive 8b/10b codes. 3.3.2 srio alignment after sync, the lane alignment must be completed. this is accomplished by sending continuous /a/s on all lanes. the / a/s are counted until lane alignment is accomplished. th e state machine for the "a" counters is shown on page vi-60 of the lp-serial specification for rapidio. the state machi ne is tolerant of an occasional /invalid/ code group, and will increase or decrease the state of alignment (not_aligned to aligned_3) based upon the successful transfer of /a/'s on the lanes. a fully successful alignment would enable the 4x mode of srio. if links are broken and/or alignment is not possible, the interface will be required to operate with a single link (lane 0 or 2).
18 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes 3.3.3 srio mode initialization once sync and alignment is accomplished, the srio controlli ng device will search for the serb. the steps of the search include silent, seek, and then discovery. once discovery is complete, the mode will be set to 4x_mode (optimum performance), 1x_mode_lane0, or 1x_mode _lane2, depending upon the success of establishing the link. the state machine for the mode is shown on page vi -64 of the lp-serial specification for rapidio. 3.3.4 srio control symbols srio requires the transmission of control symbols provid ing link status every 819.2ns or less whenever the link is otherwise idle. the control symbols are described in section 5.2 of the lp-serial specification for rapidio. these include delimiters /k28.3/ if a packet delimiter is included or /k28.0/ if there is no packet delimiter. 3.3.5 srio end-to-end retransmissions as an srio bus endpoint, the serb supports end-to-end srio retransmissions. this is required for the serb to meet the srio compliance testing as an endpoint. when s-port is acti ng as an srio slave, the serb fully acknowledges all link- to-link transactions and end-to-end transac tions per the srio specification. as an srio bus master, as would be the case with a waterlevel or doorbell master, the serb has limited capabilities. at the link level, the serb has the ability to receive acknowl edgement of all transactions at the link level and perform retrans- missions of any packets for which a retransmission has been requested. the serb does not have the ability to support end-to-end re transmissions as a bus master. when a packet is sent out from the serb as a bus master, an end-to-end response packet should be received in due time. the packet will be handled as follows: if the response is an acknowledgement -- the response will be ignored. if the response is a retransmission request - a flag w ill be set and the packet otherwise ignored. no retransmission will be attempted. if there is no response - the serb will not realize t here was no response, because it was not looking for one. 3.3.6 the serb as an srio system host the serb has no ability to act as a host in an srio system. the serb does have the ability to act as a bus master on occasion and will take control of the bus to accomplish the transmission of selected data items or perform selected func- tions. the serb does not have the ability to control a system or fully interact and interpret the actions of other devices in the system. bus mastering is limited to the transmission of the designated data. 3.4 the srio packet srio has a defined packet structure for each type of pa cket. the srio specification should be referenced for a complete description of srio packets and their architecture. pa cket aspects that are significant in the serb are described here for clarity, but the srio specificati on overrides in the event of a discrepancy. figure 3 generic srio request packet looking at figure 3 , the srio packet contains the following items: physical layer defined header, shown in figure 4 . the transaction type, tt, that defines 8 or 16 bit device id fields, shown in figure 5.
19 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes the ftype, which defines the type of packet being sent. the types are shown in section 3.4.4 . the target address, a.k.a destination id. this will be 8 bits or 16 bits, depending upon the state of tt. the source address, a.k.a source id. this will be 8 bits or 16 bits, depending upon the state of tt. the transaction, which is dependent upon the packet ft ype. the supported transactions are described individually. 3.4.1 srio physical layer header the srio physical layer header is shown in figure 14. the va rious fields are defined in the srio physical layer 1x/4x specification. the srio priority is the priority of the pa cket during transmission. the contents of the physical layer do not go beyond the interface, except the packet priority (pri) may be dictated for any transmitted packet. in the serb, there are two methods for setting the priority. if a transmitted packet is a response to a received packet, t he srio response priority will be one priority level higher than the priority of the request packet, up to the maximum priority. if the transmitted packet is being initiated by the serb, the priority of the packet will be dictated by the serb. in most cases, the priority will be dictated by the "case scenario". figure 4 srio physical layer header 3.4.2 srio physical layer crc crc-16 accompanies all srio packets and is defined in the srio physical layer 1x/4x specification. the location of crc within the packet is shown in figure 3 . 3.4.3 srio transport layer header (8/16 bit device ids) during srio "bring up", the serb shall support both 8 and 16 bit device id fields. once configured as either 8 or 16 bit, the serb does not support the other type and will drop packets once configured. considering that the only packet type supported is the type c onfigured, the tt bits within the packet are not useful. the serb insures that the proper tt bits are included in every packet sent. incoming packet tt bits are a "don't care". within the srio packet, the tt (transaction type) is us ed to identify the size of the fields as shown in figure 5 . figure 5 transaction types (8 or 16) the source and destination ids in the srio packet will be eit her 8 or 16 bit as configured. every srio packet that the serb generates contains a target id that has been generated from one of following ways: the packet is in response to a request. the target id is the source id of the requestor. the packet is generated by the serb through a "case scenario". the target id is included in the case scenario. any packet that is generated by a case scenario will use the source id of the queue to send the packet. any flag associated with a queue will use the source id of the queue to send the doorbell. tt definition 00 8-bit device id fields 01 16-bit device id fields 10 reserved 11 reserved ackid rsrv = 00 pri o 5 2 2 cr f 1
20 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes any packet that is generated by the serb that is unrel ated to a particular queue (such as a link error) will use the device id of the serb as the source id. 3.4.4 srio request packet types (ftype 0 - 11) within the srio specification, 16 packet types may be fo rmed. packet types "type 0" through "type 11" are request packet types. packet types, "type 12" through "type 15" ar e response packet types. many of the packet types are reserved. the serb has limited srio functionality, but should be able to imitate any type of command. the serb initiates commands through the case scenario. case scenarios have the ab ility to initiate any type of command by simply entering the correct ftype and the rest of the srio header as desired. the required data may be appended as needed. the serb fully supports only selected srio commands. the user needs to be aware of the limited serb functionality, but may be able to pass commands outside the serb limits if the usage and expectation of the commands fits within the limits of serb capabilities. following are the srio commands serb is capable of supporting: swrite (type 6) car/csr (type 8) doorbells (type 10) messages (type 11) (no defined message) following are the srio commands supported in next phase of serb: nread (type 2) nwrite (type 5) nwrite_r (type 5) the packet types are described in the rapidio interconnect specification, part 1: input/output logical specification in chapter 4. the following is a list of the packet types and the level of support the lite protocols shall offer. type 0 packet format (implementation defined) type 0 packets shall not be used on the serb. type 1 packet format (reserved) type 1 packets are not defined in the srio spec and shall not be used in the serb. if received, they are simply passed unaltered at the logical level. type 2 packet format (request class) type 2 packets are described in section 4.1.5 of the srio spec. type 2 is used for nread and atomic in standard srio. the serb does not support neither nread nor atomic packet format. type 3-4 packet format (reserved) type 3 and type 4 packets are not defined in the srio spec and shall not be used in the serb. if received, on the srio port with an serb destination id, an error message shall be sen t. when a case scenario is loaded with type 3 or 4, the type shall be passed along with any data. no further interpretation should be needed. type 5 packet format (write class) type 5 packets are described in section 4.1.7 of the srio spec. type 5 is used for nwrite, nwrite_r, and atomic in standard srio. as with type 2 packets, the priority must be identified so it can be passed. type 6 packet format (streaming-write class) type 6 packets are described in section 4.1.8 of the srio spec. type 6 has only one function (swrite), which is limited in scope with no response needed. therefore, the entire swrite packet must be passed unaltered, except for the addition of a priority designation. the ppsc generates swrite packets, so the primary packet the serb will see in pps applications is swrite. the serb must accept swrite packets as they are receiv ed, because the pps has no backpressure mechanism and a delay in packet acceptance will mean packet loss.
21 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes type 7 packet format (reserved) type 7 packets are not defined in the srio spec and shall not be used in the serb. if received, on the srio port with an serb destination id, an error message shall be sent. when a case scenario is loaded with type 7, the type shall be passed along with any data. no further interpretation should be needed. type 8 packet format (maintenance class) type 8 packets are described in section 4.1.10 of the srio input/output logical specification. these packets are the cars and csrs necessary for programming and reading the status/capability of the serb. the serb must fully support type 8 packets. type 9 packet format (reserved) type 9 packets are not defined in the srio spec and shall not be used in the serb. if received, on the srio port with an serb destination id, an error message shall be sent. when a case scenario is loaded with type 9, the type shall be passed along with any data. no further interpretation should be needed. type 10 packet format (doorbells) doorbells are not defined in the srio, part 1, "input/output logical specification", but are listed as "reserved" in section 4.1.11 of that spec. the type 10 packets are defined in the part 2, "message passing logical specification". the serb shall issue doorbells as defined in section below. type 11 packet format (messages) there is no use identified for type 11 packets. these packets normally carry non-doorbell messages. these packets are also considered "reserved" in the "input/output logical specification", but are defined in the "message passing logical specification". 3.4.5 srio response packet types (ftype 12 - 15) within the srio specification, packet types, "type 12" through "type 15" are response packet types. of the response type packets, all are reserved except packet type 13, which will be used for all response packets. if a response packet is received with a type other than ftype 13, the packet shall be ignored and an error flagged. type 13 packet format (response) ftype 13 packets are defined in the srio part 1, "input/output logical specification" in section 4.2.3 . the serb fully supports ftype 13 packets. 3.4.6 srio transaction ids every srio transaction must have an id that cannot repeat it self within a designated time. that designated time is the time that a packet may remain alive, including all block ages, retransmissions and acknowledgements. in the case of the serb, retransmission capabilities beyond the link level are not supported, and therefore the transaction id is not used. regardless, the serb must handle incoming transaction ids and generate outgoing transaction ids. the serb will attempt to categorize outgoing transaction ids. within the serb there are multiple sources of packets, where a queue may be generating packets, plus the device itself may generate packets. in some cases, one part of the device may not know what other parts are doing. source id, destination id, and transaction id all are us ed to identify a unique packet. in addition, response packets are identified as a "response". using all of these identifying markers guarantees that the serb is not capable of generating a transaction id that would interfere with those generated by another entity. the following items describe the use of transaction ids within the serb. incoming transaction ids will be returned with any re sponse packets. this includes any response messages, responses to nwrite_r and other packets that require responses. every transaction generating portion of the serb will hav e it's own unique block of transaction ids to loop on. the transaction id includes the source id of the transacti on, so we will not be interfering with other devices in the system generating transaction ids. there will be 32 transaction ids allocated to every srio packet generating entity within the serb. the doorbells will be allowed more, since there may be more active at a time.
22 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes the transaction ids are allocated per figure 6 . figure 6 transaction id range for srio packet generating entities source id, destination id, and transaction id all are used to identify a unique packet. if this includes the transaction type or some additional id, the problems of multiple ident ical transaction types would be solved. response packets are identified as response packets, which identify the originator of the request, the source id of the responder and the transac- tion id. combining these identifies a unique packet despite the possibility of otherwise conflicting transaction ids. 3.4.7 srio packet blockage and priorities the serb is not a switch and should not be involved in blocking packets. despite this, the serb may be unable to transmit packets or packets may be blocked by downstream devices, requiring the serb to hold and retransmit packets. when connected to the pps, the serb should not be reorder ing packets based upon priority, because packets are issued based upon time in the buffer and not priority. when the serb is used in non-pps applications, it may be necessary to transmit packets based upon priority. blocked packets would be held and transmitted after subsequently rece ived higher priority packets have been transmitted. in this situation, blockage may develop if the inflow to the serb exceeds or equals the outflow. typically higher priority packets would be initiated for command and symbol passing. 3.4.8 the srio write packet, type 5, special considerations the serb may receive and issue both type 5, nwrite and nwrite_r packets. the serb has no ability to issue or receive any of the three atomic packets. the wrsize acco mpanying the data will be stored as part of the packet header in the serb to allow correct identification of the packet length for subsequent transmission of the packet as the packet leaves the serb. srio type 5 packets assume the recipient device is addre ssable as a side address memory. the serb is a fifo and will store the data seqentially and transmit data sequentially, regardless of the address accompanying the data. the address will be stored as part of the packet header in the serb, and may be used when the packet is again transmitted. despite not using the addresses for data storage, the addresses are used in some applications to detect missing packets. 3.4.9 the srio maintenance packet, type 8, special considerations the srio maintenance packet is a type 8 packet and is used for programming and/or reading the cars and csrs. in addition, the port-write maintenance packet may be generated as an error response as defined by the srio error manage- ment specification. the srio maintenance packet allows in-band control of the serb configuration. the rio specifications define a number of registers for end-point devices, which is described in the register section. srio maintenance packets are type 8 packets and have the ftype field set to 1000b. these packets are described in section 4.1.10 of the srio input/output logical spec. in additi on, information on the tt and hop count can be found in section 1.3 of the common transport specification. an example of the structure of a type 8 packet is shown in figure 7 . the configuration registers are all 32 bits or less, and all pa ckets will carry 32 bits regardless of whether all 32 bits are needed. id range srio packet generating entity 31-0 queue 0 output 127-32 reserved for future use 159-128 device id of the serb 255-160 doorbells and reserved
23 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes figure 7 srio maintenance request packet (type 8) ackid = transaction id for link acknowledgements crf = critical request flow, not used in serb prio = packet priority tt = transaction type, 00 = 8 bits, 01 = 16 bits ftype = 1000, for a type 8 maintenance packet target id = the destination id of the serb, is 16 bits if tt = 01 source id = the id of the sending device, is 16 bits if tt = 01 transaction = specifies whether request is read, write an d/or response, see sect 4.1.10 of srio input/output logical spec rdsize/wrsize = see sect 4.1.2 of srio input/output logical spec srctid = the transaction id for srio end to end retransmissions hop count = not important to an end point. config_offset = the configuration register address wdptr = part of rdsize/wrsize payload = 32 bits of data destined to be written to the designated register crc = 16 bits of crc the srio maintenance request packet will receive a response packet as shown in figure 8 . the response will be returned to the sender of the request and include a "status" of the request. the status is identified in section 4.1.10 of the srio input/output logical spec. the serb shall observe that 0000b indicates "done" and 0111b indicates "error". figure 8 srio maintenance response packet (type 8) other than the status field of the packet, the fields serv e the same function as the request packet or are unused. upon a read request, the payload is the data content of the sele cted configuration register. when initiating a maintenance response packet, the hop count will be set to 0xff. the fields of the response packet are as follows: ackid = transaction id for link acknowledgements crf = the incoming crf is returned in the response prio = increased to one higher than the request tt = same as the request ftype = same as the request (8) target id = the source id of the request (a simple swap) source id = the target id of the request (a simple swap) transaction = specifies whether request is read, write an d/or response, see sect 4.1.10 of srio input/output logical spec status = 0000b means done, 0111b means error 0 1 2 3 4 5 6 7 8 9 10111213141516171819202122232425262728293031 wdptr config_offset config_offset crc payload source id hop count target id payload rsrv crf tt transaction rdsize/wrsize srctid prio ftype ackid rsvd 0 1 2 3 4 5 6 7 8 9 10111213141516171819202122232425262728293031 wdptr config_offset config_offset crc payload source id hop count target id payload rsrv crf tt transaction rdsize/wrsize srctid prio ftype ackid rsvd
24 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes srctid = the transaction id for srio end to end retransmissions (generated at the interface) hop count = set to 0xff to initiate the hop count payload = 32 bits of data read from the designated register crc = 16 bits of crc 3.4.10 virtual channel handler there is no virtual channel handler in the serb. virtual channels do not appear beyond the srio interface and have no affect on serb operation. 3.5 srio control symbols the srio control symbols are described in the srio part 6: 1x/4x lp-serial physical layer specification in chapter 3. of particular note, these symbols are used to acknowledge al l srio packets. the serb shall support the following stype 0 control symbols. packet accepted packet retry packet not accepted status link response these control symbols shall be used to acknowledge all incoming srio packets and doorbells. outgoing packets and doorbells shall expect a response and report errors when they occur. 3.6 use of crc and crc errors the serb shall have the capability of using crc-16 and is defined in the srio "1x/4x lp-serial physical layer specifi- cation" in section 2.4.2 . the following rules dictate uses of crc within the serb: crc will be crc-16 with two bytes in size. crc errors shall be counted. the counts shall be st ored and readable through the configuration registers. if retransmission is turned off, a packet with crc errors shall be dropped. there is no indication a bad packet was received. the crc error will be logged. the user may use higher level detection to retransmit a section of data. all crc errors will set the error flag and may cause interrupts or doorbells per the flag configuration. srio contains crc in all packets. crc suppression is used with the pps. the minimum packet size when retransmit is turned on is 8 bytes payload. 3.7 parallel port interface the p-port is a standard parallel interface that is used to drive qdrii sram devices. it has a 36-bit data bus, and other control signals that may be connected to a standard qdrii memory interface. the serb parallel port options: the serb may act as a fifo controller, using an exter nal qdrii-b4 x36 memory as extra storage space that may be allocated to the internal fifo queue as desired. p-port may be disabled, either by a pin, or by programming an internal register. the definition of the p-port interface in this specificati on is guidance only. the overriding requirement is that the serb must connect to a qdrii-b4, x36 device.
25 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes 4.0 data handling within the serb the s-port on serb has the ability to act as an srio endpoi nt or as an srio bus master. when the serb is outputting to an srio port, the queue holds the output packet routing in formation designating the fi nal destination for the data. in the pps application, the serb will typically act as an srio endpoint (slave), and will respond to commands received through the pps. in the event that there is an active waterlev el = watermark, the serb shall become the srio bus master to send the multicast packet to the pps. 4.1 inputting data to the queue incoming serial data must be directed to a queue upon entry into the serb. the incoming packet data carries an identi- fier that selects a "case scenario" for the data that includes the routing information. in srio, the source id of the data selects the "case scenario" for the data. this is designated at " case scenario mode ". 4.1.1 command input buffer there is an input buffer on the serb that is capable of stacking a small number of commands. there is a separate buffer for read and write commands. it should be noted that co mmands may become blocked by activity within a queue in the serb. 4.1.2 output buffer there is an output buffer that is capable of stacking output packets on the serb. in the event that multiple output packets become stacked within the buffer, the higher priority packets will be sent first. a packet that is blocked on the bus for any reason, will prevent the transmission of subsequent same priority packets and lower priority packets until the blocked packet successfully sends, or is discarded. 4.1.3 writing more data than can accept whenever an attempt is made to write more data to queue than there is space available to accept, the serb will go through the following stages: when the queue is full, a full flag will be set. the flag may then send any interrupts or doorbells to unmasked locations. the incoming data will be accepted in full packets and fill the input buffer on the fifo port. if the input buffer contains data that it cannot flush into the queue, the data will sit there, preventing the port from writing to the queue. priority and maintenance packets will not be blocked, but data packets will be blocked if the input buffer also overflows, the incoming packets will be rejected. only full packets will be accepted. if there is not room to store a complete packet, the entire packet will be rejected. the sender will be notified of the packet rejection. once the full queue empties enough to allow the data in the input buffer to flow into the queue, the input buffer will again be free to accept more data. space available the space available flag is located in the full flag register. it is assumed that if multiple sources are writing to the serb, they will poll the space available register to see how mu ch room is available for writ ing. when the space available flag toggles, the flag will be sent to the destination id within the register and to the port designated by the mask registers. any multicast will be the responsibility of the user. 4.2 outputting data from the queues the queue output is dedicated to a port and cannot be reconf igured. the queue is configured with a "case scenario" that dictates a destination to which the data is sent. the sendi ng of data is triggered by a wate rlevel (event). the configu- ration registers are used to set up the output mode.
26 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes 4.2.1 burst write start/stop address the serb has the ability to pass large quantities of data with minimal overhead. data can be passed from srio to down stream rio system memory address as either an swrite or nwrite type packets. to start the data burst, the starting srio memory address should be loaded into the case scenario start address register , along with the case scenario stop address register and an indication of whether to wrap or stop when hitting the maximum address. case scenario next address register initially starts off with same value as the start address and increments by the quantity of data transmitted with every packet until reaching stop address. if a doorbell or interrupt is desired, that may also be programmed. the configuration is "case scenario" based. the start, stop c ounter, and wrap/stop bits are all configured with the ?case? in the configuration register. therefore any data sent to this case, will increment the counters and addresses checked. it is assumed that the user will be responsible for maintaining dat a integrity, and will probably use the case for one source of data only. the serb will form srio packets, append the incrementing memory address and send the data out as an srio memory data. the memory addresses will continue to increment wi th subsequent data until all data is transmitted and the port is reconfigured or the address is reset to a new location. stop/wrap on memory write once sufficient data has entered the serb to cause the srio memory address to reach the stop address programmed into the configuration register, the serb will do the following: the serb set the "mem stop" bit in the flag register. unmasked doorbells and interrupts will be sent. the case scenario will be checked for the wrap/stop bit setting. ? if stop, the remainder of the packet will be trans mitted. stop condition must be cleared before any more data can be transmitted. ? if wrap, the address will reset to the start address afte r the overflow packet is fully transmitted. there will be no attempt to perform the wrap in the middle of a packet. it is the user's responsibility to insure that wrap boundaries concur with packet boundaries. 4.3 use of acknowledgements srio has requirements for acknowledgements that must be obs erved by the serb and are described in the srio spec- ification. both the ability to enable ack/nack and the time-out associated with packet failure may be set by programming the device configuration registers. the receipt of a nack or the failure to receive an ack within the allocated time will trigger the retransmission of all packets sent after receipt of the last ack. when configured to require packet acknowledgements, the following rules apply: packet is sent with an identifier in the header additional packets may be sent before acknowledgement is received packet identifier is incremented for each packet (and wraps) good packets must be concluded with the end of good packet (egp) marker if a known bad packet is sent, it should be marked end of bad packet (ebp) marker. once a full packet is received, the receiving dev ice must send an acknowledgement or a rejection notice. if sender times out without an acknowledgement, the packet and all subsequent packets are sent again. if rejection notice is received, packet must be retransmitted and all subsequent packets are retransmitted. packet is rejected if link errors, crc errors, or ebp code is received if the fifo fills due to the inability to successfully transmit, it indicates a link down and appropriate flags and priority packets sent (if possible). note that link level transmissions require that packet acknowledgements be received in the order sent. if a packet is not acknowledged, or acknowledgements are received out of order, it is necessary to retransmit all packets starting after the last packet for which a valid ack was received. srio link acknowledgements require acknowledgments in t he order packets were transmitted, but end-to-end acknowl- edgments may be received in any order. ack and nack are performed through link management packets and are not priority packets. ack and nack may only be used when "retry-on-error" is enabled.
27 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes 4.4 idles when the s-port is not sending packet data, 8b/10b idles shall be transmitted, along with any link maintenance packets needed per the protocol spec. idles received, will be ignored and not result in data being stored within the serb. 4.5 case scenarios the "case scenario" is method used to generate the srio packet headers when data is transmitted out of the serb. the case scenario is established to route every srio data packet that is originated by the serb. a single queue may have data intended for several different destinations as defined by the case scenario. the case scenario may be programmed to be any srio comm and type followed by data, allowing fairly sophisticated command generation with little overhead. while the serb may progr am any command into the case scenario, it is not guar- anteed that the serb is capable of fully executing more than the designated command types. the user may be able to use this feature to extend the serb capabilities. the "case scenario register" must be programmed before use. every data packet that leaves the serb must contain an srio packet header. the following are the rules describing "case scenario". case scenario is programmed into the configuration registers. every data packet originated by the serb must use a case scenario ? srio response packets do not use case scenarios ? srio doorbells, messages, and other packets do not use case scenarios the queue is programmed to always select a case scenario for all data that leaves that queue. the destination id is used to route the packet to the queue. 4.5.1 srio destination ids for queuing incoming data the serb itself has a device destination id, and any incoming srio packets that do not contain data (e.g. configuration register updates), should use this device destination id. the device destination id is further described in the configuration registers section. it is searchable on the srio bus and is programmed during the srio "bring up". the queue may be programmed with a destination id in the c onfiguration register (separate and distinct from the device destination id). this destination id is not searchabl e and not programmed in accordance with the srio "bring up" specification. instead, the register must be programmed using the same methods as most of the other configuration regis- ters. any data coming over the srio port, carrying a destinati on id that matches the destination id for the queue will be loaded into that queue. the destination id is an eight bit designation within t he srio packet header. the destination ids programmed in the configuration registers are also eight bits. the programmed des tination id will be used as the source id during srio trans- mission. figure 9 below shows the location of the destination/target id and the source id in a typical srio packet. figure 9 typical srio packet showing lo cation of source and destination ids destination ids are the means of communication within an srio environment. it is required that every srio packet have a destination id and a source id.
28 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes 4.6 waterlevel and watermarks in the serb, the "watermark" is a programmable event tri gger threshold for the data level associated with a queue. the term "waterlevel" refers to the actual data level within a queue, regardless of whether a "watermark" is used. when the waterlevel in the queue reaches the watermark, an event w ill take place, depending upon the configuration. the waterlevel and watermarks are used primarily as an indicator to control data flow within a queue. the waterlevels are different than the paf and pae flags, because pae/paf flags deal in increments of total memory space (1/256th of the queue total) and do not deal with actual dat a counts. waterlevels actually count packets or bytes as designated. 4.6.1 waterlevel controls waterlevels are primarily controlled in the configuration regi sters. the following items are available for controlling the waterlevels: data in queue is held in packets. waterlevel - a counter that holds the actual data level in a queue. the count will be in packets. watermark - this word holds the trigger point for the waterlevel. when the waterlevel reaches this point, the flag will be set. the flag may cause other events to occur (doorbells, interrupts, etc.) a single packet at a time will be sent in their original si zes. packets will continue to be sent, until the waterlevel drops below the watermark. the remaining data will be held in the queue. space available - this is a word in the waterlevel regi ster that indicates how much space is remaining in the queue. the space is in packets. the value of the counter is the total capacity of the queue minus the number of bytes already consumed. it should be noted that when operating as a waterlevel ma ster, the "master mode" only affects the queue output. it is still possible to receive write commands on the queue input. 4.6.2 example uses of waterlevels there are several possible uses of waterlevels and waterm arks. a few of the suggested applications are as follows. stable data level in queue this application allows the steady maintenance of a data level in a queue. as data is received, it is stored in the queue until the data level reaches the watermark. upon the waterlevel reaching the watermark, for every packet received, the queue will transmit an equivalent data item. the following items set up this scenario: the queue is set up to be a master the waterlevel is programmed to count packets the watermark is set to the desired number of packets to be held within the queue at all times the queue sits idle when the packet within the queue is less than the watermark. packets are received, but not transmitted if the waterlevel reaches or exceeds the watermar k, the queue will transmit enough packets to bring the waterlevel back below the watermark. pps specific use of this scenario the basestation application that uses the pps requires that there be a specific timed delay between the serb input and output packets. the delay is dependent upon the system requirements, but once the system is configured, it remains fixed. it could be any designated delay, but the maximum in the ti d sp application is 10ms. the quantity of packets that would accumulate within the designated time frame would be dependent upon how many rf cards are used in the basestation. the pps issues packets to the serb on a stable time inte rval, meaning that by using the watermark to designate a quantity of packets, a time interval can be derived from the to tal. using the watermark to trigger packet transmissions, the serb may be used as a programmed packet delay. in the typical pps application, all packets will be identical in length and at equal time intervals. usually the pps will reform packets to all be equal in size regardless of the number of antennas, but in some (rare) pps applications that have multiple antennas, it may be possible for the pps to send packets of various sizes to the serb. this should cause no prob-
29 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes lems with the waterlevel timer if packet counts are used. it is expected that all antennas will send data at very stable rates, so the combination of two or more sending packets with different sizes will not interfere with the overall timing if the total quantity is adjusted to accommodate the combined larger number. packet ready this mode may be used to indicate that at least one packet is available in the queue for reading. the flag will toggle, indicating that one or more packets is in the queue. the following is the setup. queue is programmed to be a slave waterlevel is programmed to use packets watermark is set to desired level. the flag masks should be programmed to send the desired interrupt or doorbell to the correct recipients the flag will toggle whenever the packet count in the queue goes from zero to one. the flag will remain active as long as the packet count equals or exceeds one. space available at the inn this is the reverse of the packet ready scenario. when feedi ng data into any of the ports, it may be necessary to know that there is room to accept the packet or more data. t here are a couple of ways to for the user to accomplish this: use the same scenario as "packet ready" and but set the waterlevel to one full sized packet below the queue size. an interrupt pin could be used as a "space available" pin. there is a flag on the space available counter to indicate that there is space for one more full sized packet in the queue. this flag could be used as an interrupt to indicate when the space has fallen below the designated quantity (one packet plus some extra to accommodate laten cy in shutdown). the space available counter is in the waterlevel register. use the paf and pae flags to generate an interrupt or door bell. this would give a more general indication of the space available, while preserving the watermark for other uses. the flag of impending doom in this scenario, the watermark may be programmed more accurately than the partial flags and could be used as an almost full flag or an almost empty flag. the flag could be used to indicate to the user that immediate action must be taken to avoid overflow or underflow. 4.7 missing packet detection and packet replacement in the wireless basestation application that uses the pps, a missing packet can cause havoc to the overall system. to help overcome occasional missing packets, a missing pa cket detection and replacement can be performed. there are four configuration registers that ar e programmed by the user. the registers contain memory start address , current memory address , memory address increment , and memory stop address . it is expected in the pps applica- tion that all packets bound for a single dsp will be equal si zed and have equal address increments, allowing the memory address increment to be used to detect incoming missing packets. when a packet comes into the pps, the pps may segment the packet into 8 segments. the serb will detect missing packets through the use of the address field in the packet header. in the pps application, it is expected that the user will be performing memory writes through sequential addresses. missing packets may be detected by insuring that the firs t packet starts on the memory start address and the address associated with every subsequent address matches the previ ous packet address plus the memory address increment. in other words, the current memory address plus the me mory address increment should be the new current memory address of the next incoming packet. if a packet is missed, the address should match the current memory address plus the memory address increment added twice. upon failing that, it is assumed that more than one packet was lost, or some serious failure occurred and the flag is set in the flag register. upon a serious failure, the current memory address in the incoming packet should be loaded into to the current memory address register, and the serb will attempt to compare the new current memory address plus memory address increment with the subsequent packet address. missing packet detection requires the spacing of the addresse s to hold at least two packets. it is not expected that missing packet detection will function properly with only one packe t available. if two or more packets are missing, the missing packet detection may require the spacing of the minimum and maximum addresses to allow for storage of at least three packets between the addresses.
30 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes 4.7.1 one missing packet detected if only one packet was lost and the packet that arrived is actually the following packet (detected by the memory address), a marker shall be loaded into the queue to indicate that a missing packet was detected. the incoming packet shall also be loaded into the queue. two packets shall be trans mitted from the queue to attempt to regain the timed data flow (observing transmission rate restrict ions). no error is noted and no flag is set. when the missing packet marker reaches the output of the queue, the serb shall create a dummy packet and transmit it at the time that is designated for the original packet had it not been missing. the dsp receiving the dummy will realize it is a dummy, and can take appropriate action. it follows the nor mal waterlevel/watermark scheme for transmitting packets. if the stop address is reached, a flag event has occurred and the appropriate flags will toggle. 4.7.2 two or more missing packets detected in the event that two or more packets are missing, no atte mpt will be made to reconstruct lost packets. the missing 2 error flag shall be set, which may cause additional doorbells and interrupts. the serb shall continue to load and transmit data normally, hopefully recovering full operation after the system clears itself of defective data. 4.7.3 missing packet detection summary the summary for missing packets is as follows: the memory address of each incoming packets shall be checked to insure contiguous addresses. ? the memory increment added to the former memory address tells you what the new address should be. ? the memory increment does not change in a system, but will be different between systems. therefore, packets are known length. in the event that an address does not match, it is assumed that there is a missing packet. the memory increment will again be added to the current address and checked with the address of the incoming packet. ? if the addresses match, only one packet is missing ? if the addresses do not match, two or more packets are missing, or a serious address misalignment has occurred. if one packet is missing ? a missing packet marker is loaded into the queue ? the incoming packet shall be loaded into the queue ? two packets will automatically be transmitted based on the watermark ? the packet interval timer will limit the transmission rate to match the pps acceptance rate. ? when the missing packet location reaches the queue output, a dummy packet (a packet with all zeros in the payload) shall be transmitted to replace the missing packet if more than one packet is missing ? no changes will be made to waterlevels ? no lost packet markers shall be loaded. ? no dummy packets shall be sent ? the ?missing 2 packet? flag shall be set in the missing 2 programmable flag register. ? if the flag is unmasked, a doorbell shall be sent to the des tination id within the register. the content of the doorbell shall be the content designated in the missing 2 programmable flag register. ? the memory address of the incoming packet will be loaded into the current memory address register to attempt to realign addresses ? processing will continue as normal on subsequent packe ts, allowing the dsp to decide if action is needed at the boundary conditions where the memory address exceeds the stop address ? on wrap, if the memory increment plus the former memory address exceeds the stop address, the new address will be set to the memory start address. no packet is wrapped in the middle, but the next new packet is set to the memory start address on a wrap. ? if the next packet address does not start at the memory start address, a packet is considered missing and should be replaced. ? if a second packet fails to match the designated address (start address + increment), the packet will be handled as described above -- "if more than one packet is missing" ? the start and stop range values must be aligned to the increment boundary (a multiple of the increment). ? there must be enough space in the queue to hold more than one packet for the ?missing packet detection? to function.
31 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes 4.8 packet tally indicator in cases where the serb bursts data to one of the dsps, the dsp has no way of knowing that it has received the data. the serb has the ability to send a doorbell indicating that the designated (programmed) number of packets has been sent, so that dsp may act. bursting must be done on frame boundaries within the dsp/pps application so that the dsp receives the doorbell on the frame boundary. in pps, messages may be passed more quickly than data packets, so the message may arrive prior to the data. to avoid this, the dsp must decide what t he delay is through the system for each (data and message). the dsp may then program an offset into the serb registers and a frame size. the ti dsp has no ability to analyze the contents of a doorbell, but instead uses 6 bits of the 16 bit data field as a pointer to an interrupt. the pointer is fixed in the dsp, meaning that the pointer must be programmable in the serb to match the pointer required by the dsp. relating this to the serb, the "case scenario" is used to identify the dsp as a target. every time a "case scenario" is accessed, the counter within the case scenario shall in crement. when the count reaches the maximum programmed for that case, the serb shall send a doorbell to the destination id designated in the case scenario, and the count shall reset. the flag register may be used, except the doorbell must be sent regardless of whether previous flags have cleared. regarding the "offset", aside from initial power up/reset, it is uncertain what the trigger event is that would require an offset. therefore, the serb shall provide an offset to t he first frame count after power up and upon any reset that clears data. since the offset is contained in the case scenario, it may be accessed at any time by any of the programming sources and can be adjusted as needed. the "packet tally indicator" frame size, frame offset, count, and whether to send a doorbell are contained in each case scenario. 4.9 packet interval timer the pps and potentially other devices may not have the ability to accept data at an accelerated rate. the pps processes incoming data as it arrives, limiting the amount of data that can be accepted in a burst. to solve the problem, a "packet interval timer" has been added to the serb to regulat e the spacing between packets going out the port. there is a separate programmable timer for data packets and priority pa ckets, since they take different routes through the pps. every time a packet is sent, the timer is reset and then counts down. another packet of the same type may not be sent until the timer times out. 4.10 protocol translation through the srio port on the serb, data may be written to or read from the fifo. the port also has the capability of initiating data transfers (as a master), and writing data out of the port to another location. in addition, serb control words may be written into the serb through the port to configure or to read the status of the device. when using the serb in two srio domains, translation iss ues arise. it should be noted that the serb has limited trans- lation capability. its primary translation function is receivi ng data, storing data, and subsequently transmitting the data. th e ability to pass commands through the serb is limited. to insu re compatibility, there are constraints upon the data. the serb will handle all link maintenance functions, required responses, retransmissions, and other negotiations. in the pps application, the serb is essentially an srio to srio translator. the serb receives data in packet form, stores it, and then transmits it at the designated time on the same port. the incoming packet must match the outgoing packet in size. pps uses only a designated (programmed) packet size.
32 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes
33 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes 5.0 doorbells and interrupts interrupt pins and packetized doorbells are used to pass interrupts and messages out of the serb. outgoing doorbell packets and interrupts are generated by flags. a flag is considered any event that results in a bit being stor ed in the "flag register". the content and masks for the flag registers are detailed in flag and flag mask register section. events at these locations will cause a flag to be stored at the designated location within the flag register as they occur. in addition to simply residing within the flag register, any fl ag may cause an interrupt, notifying external devices that a flag event has occurred. this interrupt is considered a "doorbell" and may be issued in one of the following ways: external output pin toggling (two pins, each with a mask). srio type 10 packets sent over s-port. each flag register has four mask registers designating whic h flags should cause the associated "doorbell" or interrupt on the port. a violation of any unmasked flag shall cause the des ignated interrupt to occur. of the four mask registers, mask 1 is associated with s-port and will cause doorbells to be sent. mask 3 and mask 4 are not associated with a port and will cause external interrupt pin 0 and interrupt pin 1o toggle respectively. mask 2 is reserved for future use. as a default, the flag register mask will not generate any interrupts (full mask). interrupt generation must be programmed by the mask registers. in the event that multiple flags toggle, the interrupt s/doorbells will be generated based upon the priority programmed in the flag registers. in the event that flags have the same priori ty, the flags will be handled in the order they occurred. in th e event that multiple flags with the same priority toggle si multaneously, the flag with lowest address will have priority over flags with higher addresses. 5.1 doorbell characteristics when a flag causes a doorbell, the doorbell includes the following: the register number containing the toggled flag the flag number within the register that toggled the entire unmasked content of the flag register (flags only) srio doorbells are limited to a 16-bit payload. 5.1.1 srio flag doorbell packet an 8-bit srio doorbell packet is shown in figure 10 . the target id of the srio doorbell is programmed into the flag register causing the doorbell. the source id will be the sour ce id of the doorbell in the serb. if the doorbell is generated by a queue, the destination id associated with the queue will be the source id for the doorbell. if the doorbell is generated by something other than a queue (e.g. a link error), the srio generat ed destination id of the serb shall be used as the source id of the doorbell. figure 10 srio doorbell packet
34 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes srio 8/16 bit destination ids for srio doorbells while typically all transactions with the serb will be either 8 or 16-bit addresses exclusively, the serb may be used in systems that mix 8 and 16 bits. every flag register contains 16 bits that may be used as a destination id. to define the usage of 8 or 16 bits, every flag register that is capable of sending a doorbell contains a "tt" designation in the flag register that indicates whether the full 16 bits should be us ed as a destination id for the doorbell or only the 8 lsbs. the srio packet will be formed with the address, based upon the tt bit. in no case will a transaction contain an 8-bit source id and a 16-bit destination id (or the reverse) in the same doorbell. this does not exclude the possibility of a queue using 8 bits as the destination id for the queue, and then generating a doorbell to a 16-bit destination. it does mean that if a user is trying to mix 8 and 16 bit destination ids, they will need to correlate the 8 lsbs for both. srio flag doorbell payload the srio flag doorbell payload is a maximum of 16 bits. the payload consists of the following 2 bits = unused 6 bits = register number of the flag that is causing the doorbell 8 bits = register contents showing the status of every flag in the register, regardless of whether the flags are masked. 5.2 external interrupt pins int(0) and int(1) each of the two external interrupt pins may be toggled by any unmasked flag. each pin has its own flag mask available allowing the user to designate the flag or combination of flags that will cause the interrupt pin to toggle. there are two types of flags indicated in the flag register , which are rt (real time) and cl (clearable) flags. when an unmasked rt flag toggles an interrupt pin, the pin will rema in active as long as the flag is active and cannot be clear, except by reprogramming the mask. when an unmasked cl flag t oggles the pin, the user may reset the flag, and the inter- rupt indication will be removed from the pin until the flag again toggles or the mask is reprogrammed. it is expected that one of the two pins will be programmed to indicate a generic flag concern, including all flags that may cause concern to the user. the second flag pin would be us ed to monitor an immediate or frequently used condition, such as "packet ready", meaning that the toggling of the flag generates immediate response without further determination concerning the cause of the interrupt. there is no ability for srio to toggle one of the interrupt pi ns directly through a command. srio may toggle a pin indi- rectly by creating a condition that causes one of the unma sked flags to toggle, subsequent ly affecting the designated pin. 5.2.1 clearing interrupt clearing an interrupt is accomplished by clearing all flags that are causing the interrupt. since multiple flags are together in a register and additional flags may toggle after a register has been read, completely clearing a register may clear unrecognized flags. the proper usage of flags and how to clear them, is described in section 8.5 , flag and flag mask registers in the notes of this datasheet. as described, writi ng a "1b" to a flag clears it. wr iting a "0b" to a flag does not affect the flag. this way, any flag may be individually clear ed or cleared in combination with other flags in the same register.
35 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes 6.0 device programming the operational setup of the serb is accomplished through the programming of the confi guration registers. during power up or master reset, the configuration registers defaul t to a known state based upon the configuration established on the hard-wired pins. after power up, the configuration regi sters may be further altered through programming. it shall be possible to hard-wire the serb to have full port functionality and be fully programmable through any of the designated programming methods without relying upon a second programming method. in the priority scheme of configuration, the hard-wired def ault pin configuration is the dominant configuration during power up or hard reset. the hard-wired inputs will be read on pow er up or reset, and shall not alter the state of the serb after completion of power up or reset. the hard-wired configuration may be overwritten through any of the programming schemes, except in a few selected cases (such as desi gnated protocol) where there is no additional programmability. once fully powered and hard reset is no longer active, the c onfiguration registers may be reprogrammed or altered by several schemes. the configuration register will retain t he last programmed configuration regardless of programming method. one programming method is not dominant over the others, except on master reset. the methods of device programming are as follows: hard wired configuration i 2 c jtag srio maintenance packets the hard-wired configuration will be the initial default setting for the serb and forced setting after hard reset. the default configurations are shown in t he configuration register section. the configuration registers for the serb are shown in section 8.2 of this datasheet. all configuration registers may be read through i 2 c, jtag, and srio protocol priority packets. in addition to the listed configuration registers, there are many registers associated with programming srio per the srio specif ication. all bits in the configuration registers are readable by any available method. bits that have restricted write access may still be read by any method. 6.1 vendor ids for srio there are three fixed device ids. these are available only when srio is active and maybe openly accessed by any of the register reading mechanisms. if srio is not acti ve, this section of the die is not powered, and the ids are not available. the srio ids are as follows: the vendor id, indicating idt (assigned by the rapidio trade association) the device id, indicating the part type the die signature, indicating date code, revisi on or other assembly specific information jtag also has a jtag vendor id. all jtag ids are accessible only through jtag. 6.2 memory map base address description srio configuration registers 0x000000 - 0x0000fc rio base feature space registers 0x000100 - 0x00053c rio extended feature space registers 0x000600 - 0x000e3c rio error management space registers serb configuration registers 0x018004 reset & command register 0x018008 serial port configuration register 0x01800c reserved for future use 0x018010 parallel port configuration register 0x018014 memory allocation register table 1 serb memory map
36 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes 0x018018 - 0x01802c reserved for future use 0x018030 lost packet replacement register 0x018034 source and destination id register 0x018038 - 0x018054 reserved for future use 0x018058 pae-paf register 0x01805c - 0x018064 reserved for future use 0x018068 - 0x018070 waterlevel/watermark control registers 0x018074 - 0x0180c4 reserved for future use 0x0180c8 - 0x0180cc mbist registers 0x0180d0 jtag device id register 0x0180d4 - 0x0183fc reserved 0x018400 - 0x018410 case scenario configuration registers 0x018414 - 0x01857c reserved for future use 0x018580 - 0x01858c missing packet detection registers 0x018590 - 0x0185bc reserved for future use 0x0185c0 - 0x0185c4 packet interval timer registers 0x0185c8 reserved for future use 0x0185cc missing packet size register 0x0185d0 - 0x0185d8 reserved for future use 0x0185dc - 0x01860c s-port packet xmt/rcv counter registers 0x018610 - 0x018c2c reserved 0x018c30 s-port serdes quad control register 0x018c34 - 0x019c00 reserved flag and flag mask registers 0x019c04 s-port link status flag register 0x019c08 reserved for future use 0x019c0c device configuration error flag register 0x019c10 srio dma status register 0x019c14 - 0x019c4c reserved for future use 0x019c50 missing packet flag register 0x019c54 - 0x019c5c reserved for future use 0x019c60 fifo queue empty flag register 0x019c64 fifo queue full flag register 0x019c68 - 0x019c9c reserved for future use 0x019ca0 dsp interrupt flag register 0x019ca4 - 0x019cc0 reserved 0x019cc4 s-port link status mask register 0x019cc8 reserved for future use 0x019ccc device configuration error mask register 0x019cd0 srio dma status mask register 0x019cd4 - 0x019d0c reserved for future use 0x019d10 missing packet mask register 0x019d14 - 0x019d1c reserved 0x019d20 fifo queue empty mask register 0x019d24 fifo queue full mask register base address description table 1 serb memory map
37 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes 6.3 configuration register programming and reset there are multiple types and severity of reset capabilities. many of the resets involve loading the configuration regis- ters, or clearing values contained in the registers. the various resets may be performed through the following mecha- nisms: external pins srio control symbols. srio type 8 maintenance packets jtag and i 2 c commands multiple types of resets may be generated using the reset me chanisms. the following items list the various resets, the mechanism(s) to force the reset, the effects of the reset and other reset information: master reset - performed after power on and anytime a full reset is needed. ? pin based reset or srio control symbol only. ? any shadow registers are programmed to the state required by the hard-wir ed configuration pins. ? all configuration registers programmed to the stat e required by the hard-wired configuration pins. ? any registers that do not have default values are cleared. ? all memory will be cleared. ? all flag registers will be cleared. all mask registers are set to fully masked. ? all error counters and status registers will be cleared (not set to a programmed value). ? all plls will be reset. ? any existing state machines will be initialized to a known state. ? any changes are immediate partial reset - performed anytime and affects all registers. (an example of this type of reset would be the changing of a port data rate). ? srio maintenance packet reset, jtag, or i 2 c based reset. this reset is performed by "hitting" the reset configuration register. ? shadow registers are not affected. ? configuration registers with shadow regist ers are programmed to the shadow values. ? configuration registers without shadow registers are cleared. ? all memory will be cleared ? all flag registers will be cleared. all mask registers are set to fully masked. ? all error counters and status registers will be cleared (not set to a programmed value). 0x019d28 - 0x019d5c reserved 0x019d60 missing packet address log register 1 0x019d64 - 0x019e0c reserved 0x019e10 tally doorbell flag register 0x019e14 - 0x019e4c reserved 0x019e50 missing packet programmable flag register 0x019e54 - 0x019e5c reserved 0x019e60 dsp interrupt mask register 0x019e64 - 0x019ecc reserved 0x019ed0 tally doorbell mask register 0x019ed4 - 0x019f0c reserved 0x019f10 missing packet programmable mask register 0x019f14 - 0x019f1c reserved 0x019f20 missing packet address log registers 2 base address description table 1 serb memory map
38 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes ? all plls will be reset. ? any existing state machines will be initialized to a known state. ? any changes are immediate, except jtag and i 2 c will perform the change at the designated command load configuration - identical to "partial re set" except ports and plls are not reset. 6.3.1 programming configuration register reset (registers without shado ws) - these resets may be performed anytime on the fly and they affect only the designated register. they are per formed by loading the indivi dual register with a new value. (example of the registers affected include the destination ids). ? srio maintenance packet. the registers may not be programmed through jtag, or i 2 c. ? shadow registers and configuration registers with shadows are not affected. ? memory is not affected ? flag registers may be individually cleared using this me thod. mask registers are part of the flag register and will be affected along with any writing to the flag registers for clearing. ? designated error counters and status registers will be cleared (not set to a programmed value). ? plls are not affected ? any existing state machines are not affected, exc ept possibly as a result of the register changing. ? any changes are immediate shadow register programming - these resets may be per formed anytime on the fly and they affect only the designated shadow register. they are performed by l oading the individual register with a new value. ? programming may be done through srio maintenance packets, jtag or i 2 c. ? only shadow registers are affected. ? memory is not affected ? flag and flag mask registers are not affected. ? error counters and status registers are not affected. ? plls are not affected ? no existing state machines are affected. ? there is no immediate effect on any configuration register from programming a shadow register. to load the results of the programming into the designated conf iguration registers, a "load configuration" reset must subsequently be performed. flag register reset - these resets may be performed anytime on the fly and they affect only the designated register. ? performed with srio maintenance packets. ? flag registers are cleared by writing to them. writi ng the wr32 bit within the register designates whether the write to a flag register is intended to alter the ent ire register, including destination ids, or simply clear flags. flags may be cleared by writing a "1" to them. any flag that is written with a "0" will remain unchanged. ? some flag registers contain real time values, indicated by "rt" in the flag register section. these values cannot be cleared except by affecting the source of the flag. a new doorbell or interrupt will not be gener- ated if the rt flag is active. ? error counters and status registers may be associated with flag registers and will be cleared if written to. ? jtag and i 2 c may read the registers, but cannot clear the flag registers, except through a load configu- ration type reset. ? any changes are immediate 6.3.2 clearing flags flags are cleared by the various "resets" associated with the serb. the methods of clearing flags are described in section 6.3, of this datasheet. in summary, any flag may be cleared by master reset, a load configuration, or by writing to the flag register. any mask register may be programmed by writi ng to it, but it won't be affected by clearing a flag register.
39 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes any "real time" flag, indicated by rt in the following flag register tables, indicates the current condition of the flag- causing event and cannot be cleared. no new doorbells or interrupts will be generated as a result of the write to a flag register containing an rt flag. to generate a new doorbell or in terrupt, at least one flag in the register must de-assert and reassert. clearable flags are indicated by cl in the following flag r egister tables. these flags assert and lock whenever a flag event occurs. they must be cleared by one of the designated re set methods. these flags represent highly transient condi- tions, so in most cases the flag causing condition has disappeared prior to the clearing. in the event that the flag causing condition is active at the time of the clearing, and the flag is immediately reasserted, a new doorbell or interrupt will be generated. 6.3.3 flag masks flag masks default to fully masked upon a master reset or load configuration reset. the flag mask registers are considered configuration registers and are individually programmed the same way as other configuration registers. the flag mask registers have no shadow registers, so they can be programmed "on the fly".
40 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes
41 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes 7.0 error management the sb handles errors in two ways. the errors are defined as either errors that fall under the ?rapidio part 8: error management extensions specification? or errors that do not. the configuration registers associated with errors are found in the rapidio part 8: error management extensions specification section 2.3 , outlines the required registers for error management. this section is focused on errors and status information in addition to the minimum required by the rio specification. 7.1 srio errors and error handling this section describes how the logical and physical layers will detect and react to rio errors. the action of the serb upon notification off any of these errors is described minimally; for detail see interrupt generation. reference rio intercon- nect specification part 8 (error management extensions specific ations) for more detail on specific errors described below. rio errors are classified under three categories: recoverable errors notification errors fatal errors 7.1.1 recoverable errors these errors are non-fatal transmission errors (such as corr upt packet or control symbols, and general protocol errors) that rio supports hardware detection of and a recovery mechanism for, as described in the rio specification. in these cases, the appropriate bit is set in the port n error detect csr. only the packet containing the first detected recoverable error that is enabled for error capture (by port n error enable csr) will be captured in the port n error capture csrs. no interrupt is generated or actions required for a recoverable error. recoverable errors are detected in the physical layer only. 7.1.2 notification errors these errors are non-recoverable non-fatal errors detected by rio (such as degraded threshold, port-write received, and all logical/transport layer (ltl) errors captured). becaus e they are non-recoverable (and in some cases have caused a packet to be dropped), notification by interrupt is available. however, because they are non-fatal, response to the inter- rupt is not crucial to port performance; i.e., the port is st ill functional. when a notification error is detected, the appropr iate bit is set in the error-specific register, an interrupt is gener ated, and in some cases, the error is captured. the degraded threshold error also causes the port to request training (parallel only) with th e hope that port performance will improve. in all cases, the rio port continues operating. notification errors are detected in both the physical and logical layer. 7.1.3 fatal errors serb detects two fatal errors: exceeded failed threshold exceeded consecutive retry threshold in these cases, the port has failed because its recover able error rate has exceeded a predefined failed threshold or because it has received too many packet retries in a row. in the first case, grio will set the output failed-encountered bit in the port n error and status csr; the rio output hardware may or may not stop (based on stop-on-port-failed- encounter-enable and drop-packet-enable bits). in the second case, rio will set the retry counter threshold trigger exceeded bit in the port n implementation error csr; the ri o hardware will continue to operate. in both cases, an inter- rupt is generated, and while the port will continue operating at l east partially, a system-level fix (such as reset) is recom- mended to clean up rio?s internal queues and resume normal operation. fatal errors are detected in the physical layer only. 7.2 system software error notification system software is notified of logical, transport, and physical laye r errors in two ways. an interrupt is issued to the local system by means of interrupt pins if enabled, or a maint enance port-write operation issued by serb. for specifics on inter- rupt mechanism, see section 5 , doorbells and interrupt of this datasheet. maintenance port-write operations are sent to a
42 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes predetermined system host (defined in the port-write target devic eid csr). serb sets the port-write pending status bit in the port 0 error and status csr. a 16 byte data payload of the maintenance port-write packet contains the contents of several csr, as shown in table below. once system software re ceives an port-write operation, it indicates that it has seen the port-write by clearing the port-write pending status bit in the port 0 error and status csr. the component tag csr is defined in the rapidio part 3: common transport specification, and is used to uniquely identify the reporting device within the system. a port id fiel d contains all 0?s indicating port 0, the logical/transport laye r error detect csr, and the port 0 error detect csr are used to describe the encountered error condition. 7.3 srio errors supported 7.3.1 physical layer errors table below lists all the rio link errors detected by the se rb physical layer and the actions taken by serb. the error enable column lists the control bits that may disable the er ror checking associated with a particular error (if blank, error checking cannot be disabled). the cause fi eld column indicates what cause fiel d will be used with the associated packet- not-accept control symbol for input error recovery. the em e error enable/detect column indicates which bit of the p0erecsr allows the error to increment the error rate counter and lock the port 0 error capture registers, and likewise which bit of the p0edcsr is set when the error has been detected. table 4 below, physical rio threshold response, lists serb behavior after exceeding certain preset limits (degraded threshold, failed threshold, retry threshold). physical rio errors detected data payload byte offset word 0x0 component tag csr 0x4 port 0 error detect csr 0x8 implementation specific portid(byte) 0xc logical/transport layer error detect csr table 2 port-write packet data payload for error reporting error error enable serb action cause field eme error type eme error enable / detect received character had a dis- parity error. enter input error stopped. enter output error stopped. 5: received invalid/illegal character delineation error de received an invalid character, or valid but illegal character enter input error stopped. enter output error stopped. 5: received invalid/illegal character the four contol character bits associated with the received symbol do not make sense (not 0000, 1000, 1111). enter input error stopped. enter output error stopped. 5: received invalid/illegal character control symbol does not begin with an /s/ or /pd/ control char- acter. enter input error stopped. enter output error stopped. 5: received invalid/illegal character table 3 physical rio errors detected
43 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes received a control symbol with a bad crc p0pcr[ccc] enables detect. enter input error stopped. enter output error stopped. 2. received a control sym- bol with bad crc received cor- rupt control symbol ccs received packet with unex- pected ackid (out-of-sequence ackid). enter input error stopped. 1: received unexpected ackid on packet received packet with unexpected ackid ua received packet with a bad crc value. p0pcr[ccp] enables detect. enter input error stopped. 4: bad crc on packet received packet with bad crc crc received packet which exceeds the maximum allowed size by the rio spec. enter input error stopped. 7/31: general error received packet exceeds 276 bytes em packet data received w/o previ- ous sop control symbol. enter input error stopped. 31: general error protocol error (unexpected packet/con- trol symbol received) pe received an eop control sym- bol when there is no packet being received. enter input error stopped. 7/31: general error received a stomp control sym- bol when there is no packet being received. enter input error stopped. 7/31: general error received packet that is < 64 bits. enter input error stopped. 7/31: general error received a restart-from-retry control symbol when in the ?ok? state. enter input error stopped. 7/31: general error received packet with embed- ded idles. enter input error stopped. 31: general error received a non-maintenance packet when non-maintenance packet reception is stopped. non-maint. packet recep- tion is stopped when ?input port enable? = 0. enter input error stopped. 3. non-main- tenance packet recep- tion is stopped not captured any packet received while port lockout bit is set. all packet recep- tion is stopped when port lock- out bit is set. enter input error stopped. 3. non-main- tenance packet recep- tion is stopped not captured received a link request control symbol before servicing previ- ous link request. not detected. received an ack (accepted or retry) control symbol with an unexpected ackid. enter output error stopped. received ack. control sym- bol with unex- pected ackid aua received packet-not-accepted ack control symbol enter output error stopped. received packet-not- accepted symbol pna error error enable serb action cause field eme error type eme error enable / detect table 3 physical rio errors detected
44 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes physical rio threshold response link_response received with an ackid that is not outstanding. enter output error stopped. non-out- standing ackid noa received an ack (accepted, or retry) control symbol when there are no outstanding packets enter output error stopped. unsolicited ack symbol ucs received packet ack (accepted) for a packet whose transmission has nor finish. enter output error stopped. received a link response con- trol symbol when no outstanding request. enter output error stopped. an ack control symbol is not received within the specified time-out interval. pltoccsr [tv] > 0 enables detect. enter output error stopped. link time-out lto a link response is not received within the specified time-out interval. pltoccsr [tv] > 0 enables detect. (re-) enter output error stopped. error error enable serb action eme error type error detect interrupt clear notification errors error rate counter has exceeded the degraded threshold. p0ertcsr[erdtt]> 0 & any bit in p0eecsr enables detect and interrupt generation. generate interrupt. parallel port will initiate maintenance training if todten bit is set. con- tinue to operate normally. degraded threshold p0escsr [ode] write 1 to p0escsr [ode] fatal errors consecutive retry counter has exceeded the retry counter threshold trigger. pretcr[ret]>0 enables detect and interrupt generation. generate interrupt. port will be in priority order consecutive retry threshold p0iecsr [rete] write 1 to p0iecsr [rete] error rate counter has exceeded the failed threshold. p0ertcsr[erftt]> 0 & any bit in p0eecsr enables detect and interrupt generation. generate interrupt. port behavior depends on p0ccsr[spf] and p0ccsr[dpe] -- port can continue trans- mitting packets or can stop sending output pack- ets, keeping or dropping them. parallel port will ini- tiate full training if toften bit is set. failed threshold p0escsr [ofe] write 1 to p0escsr [ofe] table 4 physical rio threshold response error error enable serb action cause field eme error type eme error enable / detect table 3 physical rio errors detected
45 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes 7.3.2 logical layer errors table below lists all the errors detected by the serb logi cal layer and the actions taken by serb. note that when the serb action includes sending an error response to either ul or rio, an error response is only sent if the original transac- tion was a request that required a response. otherwise, no e rror response is sent. when dealing with multiple errors, discard of packet has higher priority than error response. here, error checking is listed based on the type of transacti on and table also lists the action taken for particular error. errors for nread transaction error interrupt generated if enable bit set on ltleecsr status bit set on ltledcsr rio error response generated logical/transport layer capture register comments priority priority of read transaction is 3 bit 4: itd bit 4: itd no using the incoming rio packet, for small transport type packet; ltlaccsr[xa] = packet bits [78:79], ltlaccsr[a] = packet bits [48:76], ltldidccsr[didmsb] = 0?s, ltldidccsr[did] = packet bits [16:23], ltldidccsr[sidmsb] = 0?s, ltldidccsr[sid] = packet bits [24:31], ltlcccsr[ft] = packet bits [12:15], ltlcccsr[tt] = packet bits [32:35] for large transport type packets; ltlaccsr[xa] = packet bits [94:95], ltlaccsr[a] = packet bits [64:92], ltldidccsr[didmsb] = packet bits[16:23], ltldidccsr[did] = packet bits [24:31], ltldidccsr[sidmsb] = packet bits[32:39], ltldidccsr[sid] = packet bits [40:47], ltlcccsr[ft] = packet bits [12:15], ltlcccsr[tt] = packet bits [48:51] rio packet dropped transporttype received reserved tt received tt which is not enabled bit 28: tse bit 28: tse no same as previous entry rio packet is dropped table 5 hardware errors for nread transaction
46 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes destid destid does not match this port?s deviceid or alternate deviceid when enabled bit 5: itte bit 5: itte yes same as previous entry -- sourceid not checked for error transaction- type received rio packet with reserved ttype for this ftype bit 4: itd bit 4: itd yes same as previous entry rdsize not checked for error srctid not checked for error address: wdptr:xambs beginning address matches lcsba1csr with non 32 bit read request. (performed only when ttype == 4?b0100) bit 4: itd bit 4: itd yes same as previous entry -- header size header size is not 12 bytes for small trans- port packet or not 16 bytes for large trans- port packet. (large trans- port packet has 14 valid bytes and two bytes of 0?s. padding of 0?s is not checked). bit 4: itd bit 4: itd yes same as previous entry -- error interrupt generated if enable bit set on ltleecsr status bit set on ltledcsr rio error response generated logical/transport layer capture register comments table 5 hardware errors for nread transaction
47 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes errors for maintenance read/write request transaction payloadsize not applicable error interrupt generated if enable bit set on ltleecsr status bit set on ltledcsr rio error response generated logical/transport layer capture register comments priority priority of main- tenance read or write request transaction is 3 bit 4: itd bit 4: itd no using the incoming rio packet, for small transport type packet; ltlaccsr[xa] = packet bits [78:79], ltlaccsr[a] = packet bits [48:76], ltldidccsr[didmsb] = 0?s, ltldidccsr[did] = packet bits [16:23], ltldidccsr[sidmsb] = 0?s, ltldidccsr[sid] = packet bits [24:31], ltlcccsr[ft] = packet bits [12:15], ltlcccsr[tt] = packet bits [32:35] for large transport type packets; ltlaccsr[xa] = packet bits [94:95], ltlaccsr[a] = packet bits [64:92], ltldidccsr[didmsb] = packet bits[16:23], ltldidccsr[did] = packet bits [24:31], ltldidccsr[sidmsb] = packet bits[32:39], ltldidccsr[sid] = packet bits [40:47], ltlcccsr[ft] = packet bits [12:15], ltlcccsr[tt] = packet bits [48:51] rio packet dropped table 6 hardware errors for maintenance read/write request transaction error interrupt generated if enable bit set on ltleecsr status bit set on ltledcsr rio error response generated logical/transport layer capture register comments table 5 hardware errors for nread transaction
48 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes transporttype received reserved tt received tt which is not enabled bit 28: tse bit 28: tse no same as previous entry rio packet is dropped destid destid does not match this port?s deviceid or alternate deviceid when enabled bit 5: itte bit 5: itte yes same as previous entry -- sourceid not checked for error transaction- type received rio packet with reserved ttype for this ftype bit 4: itd bit 4: itd yes same as previous entry -- rdsize read/write request size is not for 4 bytes bit 4: itd bit 4: itd yes same as previous entry -- srctid not checked for error hopcount not checked for error config offset not checked for error error interrupt generated if enable bit set on ltleecsr status bit set on ltledcsr rio error response generated logical/transport layer capture register comments table 6 hardware errors for maintenance read/write request transaction
49 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes header size header size is not 12 bytes for small trans- port packet or not 16 bytes for large trans- port packet. (large trans- port packet has 14 valid bytes and two bytes of 0?s. padding of 0?s is not checked). bit 4: itd bit 4: itd yes same as previous entry -- payloadsize write request with payload not equal to 8 bytes read request with payload not 0 bytes bit 4: itd bit 4: itd yes same as previous entry -- error interrupt generated if enable bit set on ltleecsr status bit set on ltledcsr rio error response generated logical/transport layer capture register comments table 6 hardware errors for maintenance read/write request transaction
50 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes errors for rio write class transactions error interrupt generated if enable bit set on ltleecsr status bit set on ltledcsr rio error response generated logical/transport layer capture register comments priority nwrite_r, nwrite transac- tion has priority 3 bit 4: itd bit 4: itd no using the incoming rio packet, for small transport type packet; ltlaccsr[xa] = packet bits [78:79], ltlaccsr[a] = packet bits [48:76], ltldidccsr[didmsb] = 0?s, ltldidccsr[did] = packet bits [16:23], ltldidccsr[sidmsb] = 0?s, ltldidccsr[sid] = packet bits [24:31], ltlcccsr[ft] = packet bits [12:15], ltlcccsr[tt] = packet bits [32:35] for large transport type packets; ltlaccsr[xa] = packet bits [94:95], ltlaccsr[a] = packet bits [64:92], ltldidccsr[didmsb] = packet bits[16:23], ltldidccsr[did] = packet bits [24:31], ltldidccsr[sidmsb] = packet bits[32:39], ltldidccsr[sid] = packet bits [40:47], ltlcccsr[ft] = packet bits [12:15], ltlcccsr[tt] = packet bits [48:51] rio packet dropped transporttype received reserved tt received tt which is not enabled bit 28: tse bit 28: tse no same as previous entry rio packet is dropped destid destid does not match this port?s deviceid or alternate deviceid when enabled bit 5: itte bit 5: itte yes for nwrite_r, no for nwrite same as previous entry -- sourceid not applicable table 7 hardware errors for rio write class transactions
51 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes transaction- type received rio packet for atomic test- and-swap transaction received rio packet with reserved ttype for this ftype packet is treated as nwrite trans- action bit 9: ut bit 9: ut yes same as previous entry -- wrsize wrsize request is for one of reserved sizes bit 4: itd bit 4: itd yes for nwrite_r, no for nwrite same as previous entry -- srctid not checked for error address: wdptr:xambs nwrite_r address matches lcsba1csr with non 32 bit read request. (performed only when ttype == 4?b0101) bit 4: itd bit 4: itd yes for nwrite_r same as previous entry -- header size header size is not 12 bytes for small trans- port packet or not 16 bytes for large trans- port packet. (large trans- port packet has 14 valid bytes and two bytes of 0?s. padding of 0?s is not checked). bit 4: itd bit 4: itd yes for nwrite_r, no for nwrite same as previous entry -- error interrupt generated if enable bit set on ltleecsr status bit set on ltledcsr rio error response generated logical/transport layer capture register comments table 7 hardware errors for rio write class transactions
52 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes payloadsize payload is greater than that indicated by {wdptr:wrsize} field, payload is not double word aligned or does not have any payload. bit 4: itd bit 4: itd yes for nwrite_r, no for nwrite same as previous entry -- error interrupt generated if enable bit set on ltleecsr status bit set on ltledcsr rio error response generated logical/transport layer capture register comments table 7 hardware errors for rio write class transactions
53 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes errors for swrite class transactions error interrupt generated if enable bit set on ltleecsr status bit set on ltledcsr rio error response generated logical/transport layer capture register comments priority swrite transac- tion is priority 3 bit 4: itd bit 4: itd no using the incoming rio packet, for small transport type packet; ltlaccsr[xa] = packet bits [78:79], ltlaccsr[a] = packet bits [48:76], ltldidccsr[didmsb] = 0?s, ltldidccsr[did] = packet bits [16:23], ltldidccsr[sidmsb] = 0?s, ltldidccsr[sid] = packet bits [24:31], ltlcccsr[ft] = packet bits [12:15], ltlcccsr[tt] = packet bits [32:35] for large transport type packets; ltlaccsr[xa] = packet bits [94:95], ltlaccsr[a] = packet bits [64:92], ltldidccsr[didmsb] = packet bits[16:23], ltldidccsr[did] = packet bits [24:31], ltldidccsr[sidmsb] = packet bits[32:39], ltldidccsr[sid] = packet bits [40:47], ltlcccsr[ft] = packet bits [12:15], ltlcccsr[tt] = packet bits [48:51] rio packet dropped transporttype received reserved tt received tt which is not enabled bit 28: tse bit 28: tse no same as previous entry rio packet is dropped destid destid does not match this port?s deviceid or alternate deviceid when enabled bit 5: itte bit 5: itte no same as previous entry rio packet is dropped sourceid not applicable table 8 hardware errors for swrite class transactions
54 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes errors for maintenance response transactions payloadsize payload size is not in double word aligned, has exceeded 256 bytes or has no pay- load. bit 4: itd bit 4: itd no same as previous entry rio packet is dropped error interrupt generated if enable bit set on ltleecsr status bit set on ltledcsr rio error response generated logical/transport layer capture register comments priority response pri- ority is not higher than rio maintenance request priority bit 4: itd bit 4: itd no using the incoming rio packet, for small transport type packet; ltlaccsr[xa] = packet bits [78:79], ltlaccsr[a] = packet bits [48:76], ltldidccsr[didmsb] = 0?s, ltldidccsr[did] = packet bits [16:23], ltldidccsr[sidmsb] = 0?s, ltldidccsr[sid] = packet bits [24:31], ltlcccsr[ft] = packet bits [12:15], ltlcccsr[tt] = packet bits [32:35] for large transport type packets; ltlaccsr[xa] = packet bits [94:95], ltlaccsr[a] = packet bits [64:92], ltldidccsr[didmsb] = packet bits[16:23], ltldidccsr[did] = packet bits [24:31], ltldidccsr[sidmsb] = packet bits[32:39], ltldidccsr[sid] = packet bits [40:47], ltlcccsr[ft] = packet bits [12:15], ltlcccsr[tt] = packet bits [48:51] rio packet dropped and ignored table 9 hardware errors for maintenance response transactions error interrupt generated if enable bit set on ltleecsr status bit set on ltledcsr rio error response generated logical/transport layer capture register comments table 8 hardware errors for swrite class transactions
55 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes transporttype received reserved tt received tt which is not enabled bit 28: tse bit 28: tse no same as previous entry rio packet is dropped and ignored destid destid does not match this port?s deviceid or alternate deviceid when enabled bit 5: itte bit 5: itte yes same as previous entry rio packet is dropped and ignored sourceid does not match the request?s destid bit 8: ur bit 8: ur no same as previous entry rio packet is dropped and ignored transaction- type received rio packet with reserved ttype for this ftype bit 4: itd bit 4: itd no same as previous entry rio packet is dropped and ignored hopcount not checked for error status is not ?done? or ?error? not ?done? sta- tus for ?read_response ? transaction type with pay- load ?error? status with payload bit 4: itd bit 4: itd no same as previous entry rio packet is dropped and ignored status error response bit 0: ier bit 0: ier no same as previous entry except error capture is done from original request -- targettid no outstanding transaction for this targettid bit 8: ur bit 8: ur no same as previous entry rio packet is dropped and ignored error interrupt generated if enable bit set on ltleecsr status bit set on ltledcsr rio error response generated logical/transport layer capture register comments table 9 hardware errors for maintenance response transactions
56 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes header size maintenance read response - total payload size with done status is not greater than 4 bytes. maintenance write response - total header size is less than 12 bytes for small trans- port packet or is less than 16 bytes for large transport packet. bit 4: itd bit 4: itd no same as previous entry rio packet is dropped and ignored payloadsize maintenance write response has payload maintenance read response with done sta- tus and pay- load not matching valid request size or request size for the response is invalid. bit 4: itd bit 4: itd no same as previous entry rio packet is dropped and ignored packet response time-out response is not received by configured time. bit 7: prt bit 7: prt no same as previous entry except error capture is done from original request -- error interrupt generated if enable bit set on ltleecsr status bit set on ltledcsr rio error response generated logical/transport layer capture register comments table 9 hardware errors for maintenance response transactions
57 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes error for response transaction error interrupt generated if enable bit set on ltleecsr status bit set on ltledcsr rio error response generated logical/transport layer capture register comments priority response pri- ority is not higher than rio request priority bit 4: itd bit 4: itd no using the incoming rio packet, for small transport type packet; ltlaccsr[xa] = packet bits [78:79], ltlaccsr[a] = packet bits [48:76], ltldidccsr[didmsb] = 0?s, ltldidccsr[did] = packet bits [16:23], ltldidccsr[sidmsb] = 0?s, ltldidccsr[sid] = packet bits [24:31], ltlcccsr[ft] = packet bits [12:15], ltlcccsr[tt] = packet bits [32:35] for large transport type packets; ltlaccsr[xa] = packet bits [94:95], ltlaccsr[a] = packet bits [64:92], ltldidccsr[didmsb] = packet bits[16:23], ltldidccsr[did] = packet bits [24:31], ltldidccsr[sidmsb] = packet bits[32:39], ltldidccsr[sid] = packet bits [40:47], ltlcccsr[ft] = packet bits [12:15], ltlcccsr[tt] = packet bits [48:51] rio packet dropped and ignored transporttype received reserved tt for this ftype received tt which is not enabled bit 28: tse bit 28: tse no same as previous entry rio packet is dropped and ignored destid destid does not match this port?s deviceid or alternate deviceid when enabled bit 5: itte bit 5: itte no same as previous entry rio packet is dropped and ignored table 10 hardware error for response transactions
58 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes sourceid does not match the request?s destid bit 8: ur bit 8: ur no same as previous entry rio packet is dropped and ignored transaction- type received rio packet with reserved ttype io read response does not correspond to an outstand- ing valid io read request. io write response does not correspond to an outstand- ing valid io write request. bit 4: itd bit 4: itd no same as previous entry rio packet is dropped and ignored status io transaction - is not ?done? or ?error? transaction type of ?response_wit h_data? and status is not done. bit 4: itd bit 4: itd no same as previous entry rio packet is dropped and ignored status io error response bit 0: ier bit 0: ier yes same as previous entry except error capture is done from original request -- targettid no outstanding transaction for this targettid bit 8: ur bit 8: ur no same as previous entry rio packet is dropped and ignored error interrupt generated if enable bit set on ltleecsr status bit set on ltledcsr rio error response generated logical/transport layer capture register comments table 10 hardware error for response transactions
59 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes packet size (all non-main- tenance and non-message). write response - header size in not 8 bytes for small trans- port packet or not 12 bytes for large trans- port packet. bit 4: itd bit 4: itd no same as previous entry rio packet is dropped and ignored payloadsize io - read response - total payload is not of the size requested. bit 4: itd bit 4: itd no same as previous entry rio packet is dropped and ignored packet response time-out response is not received by configured time for packets requiring rio response. done response is not received in configured time. bit 7: prt bit 7: prt yes same as previous entry except error capture is done from original request interrupt is generated error interrupt generated if enable bit set on ltleecsr status bit set on ltledcsr rio error response generated logical/transport layer capture register comments table 10 hardware error for response transactions
60 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes errors for reserved ftype error interrupt generated if enable bit set on ltleecsr status bit set on ltledcsr rio error response generated logical/transport layer capture register comments ftype priority of main- tenance read or write request transaction is 3 bit 4: itd bit 4: itd no using the incoming rio packet, for small transport type packet; ltlaccsr[xa] = packet bits [78:79], ltlaccsr[a] = packet bits [48:76], ltldidccsr[didmsb] = 0?s, ltldidccsr[did] = packet bits [16:23], ltldidccsr[sidmsb] = 0?s, ltldidccsr[sid] = packet bits [24:31], ltlcccsr[ft] = packet bits [12:15], ltlcccsr[tt] = packet bits [32:35] for large transport type packets; ltlaccsr[xa] = packet bits [94:95], ltlaccsr[a] = packet bits [64:92], ltldidccsr[didmsb] = packet bits[16:23], ltldidccsr[did] = packet bits [24:31], ltldidccsr[sidmsb] = packet bits[32:39], ltldidccsr[sid] = packet bits [40:47], ltlcccsr[ft] = packet bits [12:15], ltlcccsr[tt] = packet bits [48:51] rio packet dropped transporttype received reserved tt received tt which is not enabled bit 28: tse bit 28: tse no same as previous entry rio packet is dropped destid destid does not match this port?s deviceid or alternate deviceid when enabled bit 5: itte bit 5: itte yes same as previous entry -- table 11 hardware errors for reserved ftype
61 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes 7.4 other serial buffer errors all errors that are not covered by the rapidio erro r management extension will be handled by the flag registers and the user programmed reporting methods (flag mask) for those flags. it should be noted that some of the srio error are also included in the flag registers and may result in repor ting by both the rapidio error management, and the normal flag mask.
62 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes
63 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes 8.0 registers the registers of the serb are grouped into f unctions. register types include the following: srio registers (cars and csrs) serb configuration registers serb error counter registers serdes control registers flag & flag mask registers in the srio world, the term csr is used for ?command and st atus registers?. these are the combination of the config- uration and flag registers. all registers are accessible by s-port, i 2 c and jtag. not all parts of the registers are necessarily accessed from all parts. the programming of the configuration registers are de scribed in the section on system initialization. when using srio, the configuration registers are accessible only th rough maintenance packets. they cannot be accessed by using nwrite, nread or swrite. as a further grouping, the electrical characteristics of t he ports and presence of external memory should remain fixed once configured, so these should be separated from configurati ons that may change. it is more likely that destination ids and other soft configurations will change, especially in la rge applications that are not adequately served by four output queues on a port. the configuration registers are broken into blocks of rela ted functions that may be read by any port and written by any port that will not kill itself in process. it should be noted that in addition to the registers shown her e, others exist that are described elsewhere and in the srio specification. an example is the error management regi sters that may be found in the rapidio part 8: error manage- ment extension specification and in the ?error handling? section of this document. 8.1 srio registers this chapter describes the visible register set that allows an external processing element to determine the capabilities, configuration, and status of a processing element using this logical specification. all registers are 32-bits and aligned to a 32-bit boundary. 8.1.1 register summary table below shows the register map for this rapidio sp ecification. these capability registers (cars) and command and status registers (csrs) can be accessed using rapidio maintenance operations. any register offsets not defined are considered reserved for this specification unless otherwise st ated. other registers required for a processing element are defined in other applicable rapidio specifications and by the requirements of the specific device and are beyond the scope of this specification. read and write accesses to rese rved register offsets shall terminate normally and not cause an error condition in the target device. writes to car (read-onl y) space shall terminate normally and not cause an error condi- tion in the target device. 8.1.2 extended features data structure the rapidio capability and command and status registers im plement an extended capability data structure. if the extended features bit (bit 28) in the processing element featur es register is set, the extended features pointer is valid and points to the first entry in the extended features data struct ure. this pointer is an offset into the standard 16 mbyte capa- bility register (car) and command and status register (c sr) space and is accessed with a maintenance read operation in the same way as when accessing cars and csrs. the extended features data structure is a singly linked list of double-word structures. each of these contains a pointer to the next structure (ef_ptr) and an extended feature type i dentifier (ef_id). the end of the list is determined when the next extended feature pointer has a value of logic 0. all poi nters and extended features blocks shall index completely into the extended features space of the csr space, and all s hall be aligned to a double-word boundary so the three least significant bits shall equal logic 0. pointer values not in extended features space or improperly aligned are illegal and shall be treated as the end of the data structure.
64 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes 8.1.3 base feature address space 8.1.4 capability registers the serb contains a set of capability registers (cars) t hat allows an external processing element to determine its capabilities through maintenance read operations. all register s are 32 bits wide and are organized and accessed in 32-bit (4 byte) quantities. cars are read-only and are big-endian with bit 0 the most significant bit. the use of cars is described in the rio input/output logical specification in chapter 5. device identity car the device identity field identifies the vendor that manufac tured the device containing the processing element. a value for the device identity field is uniquely assigned to a device vendor by the registration authority of the rio trade associa- tion. the device identity field is intended to uniquely identify the ty pe of device from the vendor specified by the device iden- tity field. the values for the device identity field are assigned and managed by the respective vendor. name: dev_id_car address: 0x00000 block byte offset register name (word 0) register name (word 1) 0x00 device identity car device information car 0x08 assembly identity car assembly information car 0x10 processing element features car reserved 0x18 source operation car destination operation car 0x20 reserved 0x28 reserved 0x30 reserved (part 11) reserved (part 3) 0x38 reserved (part 11) reserved 0x40 reserved 0x48 reserved processing element logical layer csr 0x50 reserved 0x58 load configuration space base address 0 csr local configuration space base address 1 csr 0x60 base device id csr reserved 0x68 host base device id lock csr component tag csr 0x70 reserved (part 3) reserved (part 3) 0x78 reserved (part 3) reserved 0x80 reserved (part 11) reserved (part 11) 0x88 reserved (part 11) reserved 0x90 - 0xf8 reserved table 12 rio base feature address space bit field name reset value comment 15:0 dev_vend_id 0x0038 device vendor identifier. 31:16 dev_id 0x04f0 device identifier. table 13 device id car
65 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes note: 1. the above register is described in the rio specification part 1, sec. 5.4.1 device information car the devicerev field is intended to identify the revision level of the device. the value for the devicerev field is assigned and managed by the vendor specified by the device vendor identity field. dicar is a read only register. name: dev_info_car address: 0x00004 note: 1. the above register is described in the rio specification part 1, sec. 5.4.2 assembly identity car the assyvendoridentity field identifies the vendor that manufac tured the assembly or subsystem containing the device. a value for the assyvendoridentity field is uniquely assigned to a assembly vendor by the registration authority of the rio trade association. the assyidentity field is intended to uniquely identify the ty pe of assembly from the vendor specified by the assyven- doridentity field. the values for the assyidentity field are assigned and managed by the respective vendor. aidcar is a read only register. name: assy_id_car address: 0x00008 note: 1. the above register is described in the rio specification part 1, sec. 5.4.3 assembly information car aicar contains additional information about the assembly and the pointer to the first entry in the extended features list. aicar is a read only register. name: assy_info_car address: 0x0000c bit field name reset value comment 31:0 dev_rev all 0s device revision level. table 14 device information car bit field name reset value comment 15:0 assy_vend_id 0x0000 assembly vendor identifier. 31:16 assy_id 0x0000 assembly identifier. table 15 assembly id car bit field name reset value comment 15:0 ext_feat_ptr 0x0100 extended features pointer field: pointer to the first entry in the extended features list. 31:16 assy_rev 0x0001 assembly revision level. table 16 assembly info car
66 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes note: 1. the above register is described in the rio specification part 1, sec. 5.4.4 processing element features car pefcar identifies the major functionality provided by the processing element. pefcar is a read only register. name: proc_ele_feat_car address: 0x00010 bit field name reset value comment 2:0 ext_addr_sup 3b001 extended addressing support: indicates the number of address bits supported by the pe both as a source and target of an operation. 3b001 indicates support for 34 bit addresses. 3 ext_feat 1b1 extended features: pe has extended features list; the extended features pointer is valid. 4 com_trans_sup 1b0 common transport large system support: when enabled it indicates support for 16 bit source and destination id?s. 5 crf_sup 1b0 critical request flow support: 1b0 - pe does not support crfs 1b1 - pe supports crfs serb does not support crfs, hence this bit is hard wired to zero. 6 re_trns_sup 1b0 re-transmit suppression support: 1b0 - pe does not support rtss 1b1 - pe supports rtss serb does not support rtss, hence this bit is hard wired to zero. 7 flo_cnt_sup 1b0 flow control support: serb does not support fcs, hence this bit is hard wired to zero. 8 std_rtcs 1b0 standard route table configuration support: serb does not support srtcs, hence this bit is hard wired to zero. 9 ext_rtcs 1b0 extended route table configuration support: serb does not support ertcs, hence this bit is hard wired to zero. 10 mcast_sup 1b0 multicast extension support: serb does not support multicast, hence this bit is hard wired to zero. 18:11 - 0 reserved. 19 doorbell 1b1 indicates that the rio controller supports inbound doorbells. 23:20 mailbox 4b0 mailbox 3:0: bt 0 indicates pe supports inbound mailbox 0. bit 1 indicates pe supports inbound mailbox 1. bit 2 indicates pe supports inbound mailbox 2. bit 3 indicates pe supports inbound mailbox 3. 27:24 - 0 reserved. 28 switch 1b0 indicates that the pe can bridge to another external rio interface. 29 processor 1b0 indicates that the pe physically contains a local processor that executes code. 30 memory 1b1 indicates that the pe has physically addressable local address space and can be accessed as an endpoint through non-maintenance operations. 31 bridge 1b0 indicates that the pe can bridge to another interface. table 17 process element features car
67 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes note: 1. the above register is described in the rio specification part 1, sec. 5.4.5, part 3, sec. 3.4.1, part 6, sec. 6.4.1, part 9, sec. 4.2, and part 11, sec. 3.2 source operations car srcopcar defines the set of rio io logical operati ons that can be issued by this processing element. srcopcar is a read only register. name: src_ops_car address: 0x000018 note: 1. the above register is described in the rio specification part 1, sec. 5.4.7, part 2, sec. 5.4.1, part 5, sec. 5.4.1, and part 10, sec. 5.4.1 destination operations car destopcar defines the set of rio i/o operations that can be supported by this processing element. destopcar is a read only register. name: dest_ops_car address: 0x00001c bit field name reset value comment 1:0 - 0 reserved. 2 port_wr 1b1 port write: pe support a port-write operation. 9:3 - 0 reserved 10 dbell 1b1 doorbell: pe can support a doorbell operation. 11 data_msg 1b0 data message: pe can support a data message operation. 12 nwr_w_resp 1b1 nwrite_r: pe support a nwrite_r operation. 13 strm_wr 1b1 streaming write: pe support an swrite operation. 14 nwrite 1b1 nwrite: pe support a nwrite operation. 15 nread 1b1 nread: pe support a nread operation. 31:16 - 0 reserved. table 18 source operations car bit field name reset value comment 1:0 - 0 reserved. 2 port_wr 1b0 port write: pe support a port-write operation. 9:3 - 0 reserved 10 dbell 1b1 doorbell: pe can support a doorbell operation. table 19 destination operations car
68 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes note: 1. the above register is described in the rio specification part 1, sec. 5.4.8, part 2, sec. 5.4.2, part 5, sec. 5.4.2, part 10, sec. 5.4.2 8.1.5 command and status registers the serb contains a set of command and status registers (csrs) that allows an external processing element to control and determine the status of its internal hardware. all registers are 32 bits wide and are organized and accessed in the same way as the cars. refer to table 5-2 of the rio input/output logical specific ation in chapter 5 for the required behavior for accesses to reserved registers and register bits. processing element logical layer control csr pellccsr controls the extended addressing abilities. serb will only support 34-bit addressing. pellccsr is a read only register. name: proc_elmt_ctrl_csr address: 0x00004c note: 1. the above register is described in the rio specification part 1, sec. 5.5.1 local configuration space base address 1 csr the local configuration space base address 1 command and status register specifies the least significant bits of the local physical address double-word offset for the processing elem ent?s configuration register space, allowing the configura- tion register space to be physically mapped in the processing element. this register allows configuration and maintenance 11 data_msg 1b0 data message: pe can support a data message operation. 12 nwr_w_resp 1b1 nwrite_r: pe support a nwrite_r operation. 13 strm_wr 1b1 streaming write: pe support an swrite operation. 14 nwrite 1b1 nwrite: pe support a nwrite operation. 15 nread 1b1 nread: pe support a nread operation. 31:16 - 0 reserved. bit field name reset value comment 2:0 ext_addr_ctrl 3b001 extended addressing control (read-only): controls the number of address bi ts generated by the pe as a source and processed by the pe as the target of an operation. 3b100 - pe supports 66 bit addresses 3b010 - pe supports 50 bit addresses 3b001 - pe supports 34 bit addresses (default) all other encoding reserved. 31:3 - 0 reserved. table 20 processing element logical layer control csr bit field name reset value comment table 19 destination operations car
69 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes of a processing element through regular read and write oper ations rather than maintenance operations. the double-word offset is right-justified in the register. as is the case with all registers, an external processor writing to lcsba1csr should not assume it has been written until a response has been received. name: lcl_conf_addr_1_csr address: 0x00005c note: 1. the above register is described in the rio specification part 1, sec. 5.5.3 base device id csr the srio searchable source and destination ids are contai ned in the base device id csr, and are programmed by srio according to the srio specification. there are locati ons for both 8 and 16 bit device ids as described in the rapidio, part 3, common transport specification in section 3.5.1. the serb shall allow programming of both, in order to allow both 8 and 16 bit operations simultaneously. both device ids may be read by any of the interfaces with access to the configura- tion registers. the device ids are cleared only by master reset or by a specif ic write to the base device id csr. other resets, such as load configuration will have no affect on the base device id csr. the base device id csr has no shadow register. note: this register is in the srio spec and that spec overrides this info. name: base_dev_id_csr address: 0x000060 note: 1. the above register is described in the rio specification part 3, sec. 3.5.1 host base device id lock csr the host base device id lock csr contains the base device id value for the processing element in the system that is responsible for initializing this processing element. the hbdid field is a write-once/resettable field which provides a lock function. once the hbdid field is written, all subsequent writes to the field are ignored, except in the case that the value written matches the value contained in the field. in this case, the register is re-initialized to 0xffff. after writing the hbd id field, a processing element must then read the host base device id lock csr to verify that it owns the lock before attempting to initialize this processing element. bit field name reset value comment 16:0 - 0 reserved. 30:17 lcl_base_addr 0x 0000 local configuration space base address: these bits correspond to the highest 14 bits of the 34-bit rio address space. 31 - 0 reserved. table 21 local configuration space base address 1 csr bit field name reset value comment 16:0 lrg_base_devid 0xffff large base device id: serb source/destination id is 16 bits. the base id of the device in a large common transport system. this field is valid only if bit 27 of the processing element features car is set. 30:17 base_devid 0xff base device id: serb source/destination id is 8 bits. the base id of the device in a small common transport system (rio device id) 31 - 0 reserved. table 22 base device id csr
70 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes name: host_base_dev_lock_csr address: 0x000068 note: 1. the above register is described in the rio specification part 3, sec. 3.5.2 component tag csr the component tag csr contains a component tag value fo r the processing element and can be assigned by software when the device is initialized. it is unused internally in serb. it is especially useful for labeling and identifying devices t hat are not end points and do not have device id registers. name: comp_tag_csr address: 0x00006c note: 1. the above register is described in the rio specification part 3, sec. 3.5.3 bit field name reset value comment 15:0 host_base_did 0xffff host base device id: this is the host base device id fo r the processing element that is responsible for initializing this device. only the first write to this field is accepted, all other writes are i gnored, except in the case that the value written matches the value contained in the field. in this case, the register is re-written to 0xffff. 31:16 - 0 reserved. table 23 host base device id lock csr bit field name reset value comment 31:0 comp_tag all 0s component tag: this is a component tag for the pe. table 24 component tag csr
71 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes 8.1.6 extended features register summary table below shows the extended features register map for this rapidio specification. these capability registers (cars) and command and status registers (csrs) can be a ccessed using rapidio maintenance operations. there are four types of 1x/4x lp-serial devices, as an end point devic e. serb supports an end point device with additional software recovery registers. 8.1.7 extended features address space block byte offset register name (word 0) register name (word 1) 0x100 1x/4x lp-serial register block header reserved 0x108 reserved 0x110 reserved 0x118 reserved 0x120 port link time-out control csr port response time-out control csr 0x128 reserved 0x130 reserved 0x138 reserved port general control csr 0x140 port 0 link maintenance request csr port 0 link maintenance response csr 0x148 port 0 local ackid status csr reserved 0x150 reserved 0x158 port 0 error and status csr port 0 control csr 0x160 - 0x178 reserved for port 1 registers 0x180 - 0x198 reserved for port 2 registers 0x1a0 - 0x1b8 reserved for port 3 registers 0x1c0 - 0x538 reserved for port 4 through 15 registers 0x600 error management extensions block header reserved 0x608 logical/transport layer error detect csr logical/transport layer error enable csr 0x610 logical/transport layer high address capture csr logical/transport layer address capture csr 0x618 logical/transport layer device id capture csr logical/transport layer control capture csr 0x620 reserved 0x628 port-write target deviceid csr packet time-to-live csr 0x630 - 0x638 reserved 0x640 port 0 error detect csr port 0 error rate enable csr 0x648 port 0 attributes capture csr port 0 packet/control symbol capture 0 csr 0x650 port 0 packet capture 1 csr port 0 packet capture 2 csr 0x658 port 0 packet capture 3 csr reserved 0x660 reserved 0x668 port 0 error rate csr port 0 error rate threshold csr 0x680 - 0x6b8 reserved for port 1 registers 0x6c0 - 0x6f8 reserved for port 2 registers 0x700 - 0x738 reserved for port 3 registers 0x740 - 0xe38 reserved for port 4 through 15 registers table 25 rio extended features address space
72 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes 1x/4x lp-serial register block header the port maintenance block header 0 register contains t he ef_ptr to the next ef_blk (extended features space, error management) and the ef_id that identifies this as the generic end point port maintenance block header. note that while registers defined by software assisted error recovery ar e supported, software assisted error recovery is not (these registers are included for hot insertion only); therefore, ri o is defined here as not supporting software assisted error recovery. pmbh0csr is a read-only register. name: port_maint_blk_hdr address: 0x000100 note: 1. the above register is described in the rio specification part 6, sec. 6.6.2.1 port link time-out control csr the port link time-out control register contains the time-out ti mer value for all ports on a device. this time-out is for link events such as sending a packet to receiving the corr esponding acknowledge and sending a li nk-request to receiving the corresponding link-response. the reset value is the ma ximum time-out interval, and represents between 3 and 5 seconds. name: port_lnk_to_ctrl_csr address: 0x000120 note: 1. the above register is described in the rio specification part 6, sec. 6.6.2.2 port response time-out control csr the port response time-out control register contains the time-out timer count for all ports on a device. this time-out is for sending a request packet to receiving the corresponding re sponse packet. the reset value is the maximum time-out interval, and represents between 3 and 5 seconds. name: port_resp_to_ctrl_csr address: 0x000124 bit field name reset value comment 15:0 ef_id 0x0001 extended features id: hard wired extended features id, generic end point devices. 31:16 ef_ptr 0x0600 extended features pointer: hard wired pointer to the next block in the data structure. table 26 1x/4x lp-serial register block header bit field name reset value comment 7:0 - 0 reserved. 31:8 port_link_val 0xffffff port link time-out internal value: setting to all 0?s disables the link time-out timer. this value is loaded each time the link time-out timer starts. table 27 port link time-out csr bit field name reset value comment 7:0 - 0 reserved. 31:8 port_resp_val 0xffffff port response time-out internal value: setting to all 0?s disables the link time-out timer. this value is loaded each time the link time-out timer starts. table 28 port response time-out csr
73 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes note: 1. the above register is described in the rio specification part 6, sec. 6.6.2.3 port general control csr the port general control register contains control regist er bits applicable to all ports on a processing element. name: port_gen_ctrl_csr address: 0x00013c note: 1. the above register is described in the rio specification part 6, sec. 6.6.2.4 port 0 link maintenance request csr the port 0 link maintenance request register is accessible both by a local processor and an external device. a write to this register generates a link-request control symbol on the corresponding rio port interface. care should be taken when writing this register that it is only used for hot swap and not for software assisted error recovery (which is not supported). name: p0_lnk_maint_req_csr address: 0x000140 note: 1. the above register is described in the rio specification part 6, sec. 6.6.2.5 bit field name reset value comment 28:0 - 0 reserved. 29 discover 1b0 discovered: this device has been located by t he processing element responsible for system configuration. 0b0 - the device has not been previously discovered. 0b1 - the device has been discovered by another processing ele- ment. 30 mstr_en 1b0 master enable: the master enable bit controls whether or not a device is allowed to issue requests into the system. if the master enable is not set, the device may only respond to requests. 0b0 - processing element cannot issue requests. 0b1 - processing element can issue requests. 31 host 1b0 host: a host device is a device that is re sponsible for system exploration, initialization, and maintenance. agent or slave devices are typically initialized by host devices. 0b0 - agent or slave device. 0b1 - host device. table 29 port general control csr bit field name reset value comment 2:0 cmd 3b000 command: link_request command to send. if read, this field returns the last written value. if written with a va lue other than 3b011 (reset-device) or 3b100 (input-status), resulting operation will be undefined, as all other values are reserved in the rio spec. 31:3 - 0 reserved. table 30 port 0 link maintenance request csr
74 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes port 0 link maintenance response csr the port 0 link maintenance response register is accessible both by a local processor and an external device. a read to this register returns the status received in a link- response control symbol. this register is read-only. name: p0_lnk_maint_res_csr address: 0x000144 note: 1. the above register is described in the rio specification part 6, sec. 6.6.2.6 port 0 local ackid status csr the port n local ackid status register is accessible both by a local processor and an external device. a read to this register returns the local ackid status for both the output a nd input ports of the device. care should be taken to use this register only for hot swap and not software error management. name: p0_loc_ack_stat_csr address: 0x000148 note: 1. the above register is described in the rio specification part 6, sec. 6.6.2.7 bit field name reset value comment 4:0 lnks 0x00 link status: link status field from the link-response control symbol. 9:5 acks 0x00 ackid status: ackid status field from the link-response control symbol. 30:10 - 0 reserved. 31 rvld 1b0 response valid: if the link-request causes a link-res ponse, this bit indicates that the link-response has been received and the status fields are valid. if the link-request does not cause a link-response, this bit indicates that the link-request has been transmitted. this bit automatically clears on read. table 31 port 0 link maintenance response csr bit field name reset value comment 4:0 obackid 0x00 outbound ack id: this can be written by software but only if there are no outstanding unacknowledged packets. if there are, a newly-written value will be ignored. 7:5 - 0 reserved. 12:8 oackid 0x00 outstanding port unacknowledge ackid status: next expected acknowledge control symbol ackid field that indicates the ackid value expected in the next received acknowledge control symbol. note that this value is read-only even though rio spec allows for it to be writable. 23:13 - 0 reserved. 28:24 iackid 0x00 inbound ackid: input port next expected ackid value. 31:29 - 0 reserved. table 32 port 0 local ackid status csr
75 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes port 0 error and status csr this register is accessed when a local processor or an ex ternal device wishes to examine the port error and status information. name: p0_err_stat_csr address: 0x000158 bit field name reset value comment 0 port_uninit 1b1 port uninitialized: input and output ports are not initialized. this bit and bit 30 are mutu- ally exclusive (read-only). 1 port_ok 1b0 port ok: the input and output ports are init ialized and the port is exchanging error-free control symbols with the attached device (read-only). 2 port_err 1b0 port error: input or output port has encounter ed an error from which hardware was unable to recover. once set, remains set until written with a logic 1 to clear. 3 - 0 reserved. 4 port_wr_pend 1b0 port-write pending: port has encountered a condition which required it to initiate a main- tenance port-write operation. this bit is only valid if the device is capable of issuing a maintenance port-write transaction. once set, remains set until written with a logic 1 to clear. 7:5 - 0 reserved. 8 in_err_stop 1b0 input error-stopped: input port is stopped due to transmission error (read-only). 9 in_err_enc 1b0 input error-encountered: input port has encountered (and possibly recovered from) a trans- mission error. this bit is set when bi t 23 is set. once set, remains set until written with a logic 1 to clear. 10 in_rtry_stop 1b0 input retry-stopped: input port is stopped due to a retry (read-only). 15:11 - 0 reserved. 16 out_err_stop 1b0 output error-stopped: output port is stopped due to a transmission error (read-only). 17 out_err_enc 1b0 output error-encountered: output port has encountered (and possibly recovered from) a trans- mission error. this bit is set when bi t 15 is set. once set, remains set until written with a logic 1 to clear. 18 out_rtry_stop 1b0 output retry-stopped: output port is stopped due to a retry (read-only). 19 out_retry 1b0 output retried: output port has received a packet-retry control symbol and can not make forward progress. this bit is set when bit 13 is set and cleared when a packet-accepted or packet-not-accepted control symbol is received (read-only). 20 out_rtry_enc 1b0 output retry-encountered: output port has encountered a retry condition. this bit is set when bit 13 is set. once set, remains set until written with a logic 1 to clear. 23:21 - 0 reserved. table 33 port 0 error and status csr
76 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes note: 1. the above register is described in the rio specification part 6, sec. 6.6.2.8 port 0 control csr the port 0 control register contains control register bits for the individual port on a processing element. name: p0_ctrl_csr address: 0x000158 24 out_dgrd_enc 1b0 output degraded-encountered: output port has encountered a degraded condition, meaning that the error rate counter has met or exceeded the port?s degraded error threshold. once set remains set until written with a logic 1 to clear. once cleared, will not assert again unless the error rate counter dips below the port?s degraded error threshold and then meets or exceeds it again. 25 out_fail_enc 1b0 output failed-encountered: output port has encountered a failed condition, meaning that the error rate counter has met or exceeded the port?s failed error threshold. once set, remains set until written with a logic 1 to clear. once cleared, will not assert again unless the error rate counter dips below the port?s failed error threshold and then meets or exceeds it again. 26 out_pkt_drop 1b0 output packet-dropped: output port has discarded a packet. a packet will be discarded if: 1. it is received while ofe is set and drop packet enable is set and stop on port failed is set. 2. it is received while output buffer drain enable is set. 2. it is not-accepted by the link-partner while error rate failed thresh- old trigger is met or exceeded and link-response returns expected ackid. once set, it remains set until written with a logic 1 to clear. 31:27 - 0 reserved. bit field name reset value comment 0 port_type 1b0 port type, this indicates the port type (read-only): 1b0 - port receiver/drivers are enabled 1b1 - port receivers/drivers are disabled and are unable to receive/ transmit any packets or control symbols 1 port_lock 1b0 port lockout: 1b0 - the packets that may be received and issued are controlled by the state of the ope and ipe bits. 1b1 - this port is stopped and is not enabled to issue or receive any packets. 2 drop_pkt_en 1b0 drop packet enable: this bit is used with the stop on port failed-encountered enable bit to force certain behavior when the error rate failed threshold has been met or exceeded. 3 stop_port_fail 1b0 stop on port failed-encountered enable: this bit is used with the drop packet enable bit to force certain behavior when the error rate threshold has been met or excessed. table 34 port 0 control csr bit field name reset value comment table 33 port 0 error and status csr
77 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes note: 1. the above register is described in the rio specification part 6, sec. 6.6.2.9 11:4 re_xmt_mask 0x00 re-transmit suppression mask: suppress packet re-transmission on crc error. serb does not support this feature and these bits are set to zero. 16:12 - 0 reserved. 17 enum_boun 1b0 enumeration boundary: an enumeration boundary aware system enumeration algorithm shall honor this flag. the algorithm , on either the ingress or the egress port, shall not enumerate pas t a port with this bit set. this provides for software enforced enumeration domains within the rio fabric. 18 flo_ctrl_part 1b0 flow control participant, enable flow control transactions: 1b0 - do not route or issue flow control transactions to this port 1b1 - route or issue flow control transactions to this port. (rio spec. part 9, sec. 4.3) 19 multi_part 1b0 multicast-event participant: this bit is hard-wired to 0. 20 err_chk_dis 1b0 error checking disable, this bit disables all rio transmission error checking: 1b0 - error checking and recovery is enabled 1b1 - error checking and recovery is disabled 21 in_port_en 1b0 input port enable, input port receive enable: 0b0 - port is stopped and only enabled to route or respond to i/o log- ical maintenance packets. 0b1 - port is enabled to respond to any packet. 22 out_port_en 1b0 output port enable, output port transmit enable: 1b0 - port is stopped and not enabled to issue any packets except to route or respond to i/o logical maintenance packets. 1b1 - port is enabled to issue any packets. 23 port_dis 1b0 port disable: 1b0 - port receiver/drivers are enabled 1b1 - port receivers/drivers are disabled and are unable to receive/ transmit any packets or control symbols 26:24 port_over 3b000 port width override, soft port configuration to override the hardware size: 3b000 no override 3b001 reserved 3b010 force single lane, lane 0 3b011 force single lane, lane 2 3b100 - 3b111 reserved the change of this field during normal mode may cause re-initializa- tion. 29:27 init_port_wdth hw initialized port width, width of the ports after initialized (read-only): 3b000 single-lane port, lane 0 3b001 single-lane port, lane 2 3b010 four-lane port 3b011 - 3b111 reserved. 31:30 port_width hw port width, hardware width of the port (read-only): 2b00 single-lane port 2b01 four-lane port 2b10 - 2b11 reserved. bit field name reset value comment table 34 port 0 control csr
78 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes 8.1.8 error management extensions summary error management extensions block header the error management extensions block header register cont ains the ef_ptr to the next ef_blk and the ef_id that identifies this as the error management extensions block header. name: err_mgmt_blk_hdr address: 0x000600 note: the above register is described in the rio specification part 8, sec. 2.3.2.1 logical/transport layer error detect csr this register indicates the error detected by the logical or tr ansport logic layer. multiple bits may get set in the register if simultaneous errors are detected during the same clock cycle t hat the errors are logged, or if the detected errors are not enabled for capture. ltledcsr is stored in each grio port and t he message unit, although the values in this register can differ for each port/message unit. a port?s ltledcsr cannot detect any errors if the port or the message unit has captured an enabled logical/transport layer error until the detec ted error is cleared, and likewise, the message unit?s ltledcsr cannot detect any errors if the message unit or any port has captured an enabled logical/transport layer error. software should write this register with all 0?s to cl ear the detected error and unlock the capture registers in all por ts/ message unit. undefined results will occur if this register is written or read while actual logical/transport layer errors are being detected by the port (where detect cannot occur if an error has already been detected and not yet cleared). if a port detects multiple errors in the same cycle, multiple ltledcsr bits will be set to reflect this. if one or all of these bits are enabled, capture is done on a priority basis. if prt is set and enabled, and multiple bits are detected in ltledcsr, the capture information corresponds to prt. if prt is not set or not enabled, then all set and enabled ltledcsr bits correspond to the captured packet. if more than one port or message unit detects one or more enabled errors in the same cycle, the capture registers will be saved in the top port /message unit in the pbus dai sy chain that detected an enabled error, and the set and enabled detect bits of the port(s)/message unit below will be masked from the pbus daisy chain. this means that a read of ltledcsr will only return the un-enabled set bits from any port/message unit and enabled set bits from the top port / message unit in the daisy chain with a set enabled error, and that a read of the capture registers will return the values in the top port /message unit in the daisy chain with a set enabl ed error; i.e., the set enabled detect bits will correspond to th e capture registers. name: ltl_err_det_csr address: 0x000608 bit field name reset value comment 15:0 ext_feat_id 0x0007 extended features id: hard wired extended features id. 31:16 ext_feat_ptr 0x0000 extended features pointer: hard wired pointer to the next block in the data structure. table 35 error management extensions block header bit field name reset value comment 2:0 - 0 reserved. 3 trsp_sze_err 1b0 transport size error: the tt field is nor consistent with bit 27 of the processing element features car (i.e., the tt value is reserved or indicates a common transport system that is uns upported by this device). table 36 logical/transport layer error detect csr
79 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes note: 1. the above register is described in the rio specification part 8, sec. 2.3.2.2 logical/transport layer error enable csr this register contains the bits that control if an e rror condition locks the logical/transport layer error detect and capture registers and is reported to the system host. ltleecsr is stored in all ports and the message unit name: ltl_err_en_csr address: 0x00060c 4 rtry_tres_exc 1b0 retry error threshold exceeded: the allowed number of logical retries has been exceeded. 21:5 - 0 reserved. 22 unsup_trans 1b0 unsupported transaction: a transaction is received that is not supported in the destination operation car (io/msg/gsm logical). 23 unsol_res 1b0 unsolicited response: an unsolicited/unexpected response packet was received (io/msg/ gsm logical). 24 pkt_res_tout 1b0 packet response time-out: a required response has not been received within the specified time- out interval (io/msg/gsm logical). 25 msg_req_tout 1b0 message request time-out: a required message request has not been received within the speci- fied time-out interval (msg logical). 26 ill_trans_err 1b0 illegal transaction target error: received a packet that contained a destination id that is not defined for this end point. 27 ill_trans_dec 1b0 illegal transaction decode: received illegal fields in the request/response packet for a sup- ported transaction (io/msg/gsm logical). 28 msg_fmt_err 1b0 message format error: received message packet data payload with an invalid size or segment (msg logical). 29 gsm_err_res 1b0 gsm error response: received a response of ?error? for a gsm logical layer request. 30 msg_err_res 1b0 message error response: received a response of ?error? for an msg logical layer request. 31 io_err_res 1b0 io error response: received a response of ?error? for an io logical layer request. bit field name reset value comment 2:0 - 0 reserved. 3 tran_sze_en 1b0 transport size error enable: enable error reporting when the tt field is nor consistent with bit 27 of the processing element features car (i.e., the tt value is reserved or indicates a common transport system that is unsupported by this device). table 37 logical/transport layer error enable csr bit field name reset value comment table 36 logical/transport layer error detect csr
80 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes note: 1. the above register is described in the rio specification part 8, sec. 2.3.2.3 4 re_trs_exc_en 1b0 retry error threshold exceeded enable: enable error reporting when all allowed number of logical retries has been exceeded. 21:5 - 0 reserved. 22 uns_trans_en 1b0 unsupported transaction error enable: enable reporting of an unsupported transaction error. save and lock transaction capture information in logical/transport layer device id and control capture csrs. 23 uns_res_en 1b0 unsolicited response error enable: enable reporting of an unsolicited response error. save and lock transaction capture information in logical/transport layer device id and control capture csrs. 24 pkt_res_to_en 1b0 packet response time-out error enable: enable reporting of a packet response time-out error. save and lock original request address in logica l/transport layer address capture csrs. save and lock original request destination id in logical/ transport layer device id capture csrs. 25 msg_req_to_en 1b0 message request time-out enable: enable reporting of a message request time-out error. save and lock transaction capture inform ation in logical/transport layer device id and control capture csrs for the last message request segment packet received. 26 ill_trgt_en 1b0 illegal transaction target error enable: enable reporting of an illegal transaction target error. save and lock transaction capture information in logical/transport layer device id and control capture csrs. 27 ill_dec_en 1b0 illegal transaction decode enable: enable reporting of an illegal transaction decode error. save and lock transaction capture inform ation in logical/transport layer device id and control capture csrs. 28 msg_frmt_en 1b0 message format error enable: enable reporting of a message format error. save and lock transac- tion capture information in logical/transport layer device id and control capture csrs. 29 gsm_err_en 1b0 gsm error response enable: enable reporting of a gsm error response. save and lock original request transaction information in all logical/transport layer cap- ture csrs. 30 msg_err_en 1b0 message error response enable: enable reporting of a message error response. save and lock origi- nal request transaction informatio n in all logical/transport layer capture csrs. 31 io_err_en 1b0 io error response enable: enable reporting of an io error response. save and lock original request transaction information in all logical/transport layer cap- ture csrs. bit field name reset value comment table 37 logical/transport layer error enable csr
81 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes logical/transport layer address capture csr this register contains error information. it is lock ed when a logical/transport error is detected and the corresponding enable bit is set. ltlaccsr is stored in each port and the me ssage unit, although the values in this register can differ between each port and message unit. the message unit ltlaccsr cannot lock if any port has locked; no port ltlaccsr can lock if the message unit or any other port has locked. undefined results will occur if this register is written while actual logical/transport layer er rors are being detected by the port. name: ltl_addr_cap_csr address: 0x000614 note: 1. the above register is described in the rio specification part 8, sec. 2.3.2.5 logical/transport layer device id capture csr this register contains error information. it is lock ed when a logical/transport error is detected and the corresponding enable bit is set. ltldidcsr is stored in each port and the mess age unit, although the values in this register can differ between each port and message unit. the message unit ltldidcsr cannot lock if any port has locked; no port ltldidcsr can lock if the message unit or any other port has locked. undefined results will occur if this register is written while actual logical/transport layer er rors are being detected by the port. name: ltl_dev_id_csr address: 0x000618 note: 1. the above register is described in the rio specification part 8, sec. 2.3.2.6 bit field name reset value comment 1:0 exta 2b00 xamsbs: extended address bits of the address associated with the error (for requests, for responses if available). 2 - 0 reserved. 31:3 addr all 0s address[32:60]: least significant 29 bits of the address associated with the error (for requests, for responses if available). table 38 logical/transport layer address capture csr bit field name reset value comment 7:0 src_id 0x00 source id: the sourceid (or least significant byte of the source id if large trans- port system) associated with the error. 15:8 msb_src_id 0x00 msb source id: the most significant byte of the sourceid associated with the error. this field is valid only if bit 27 of the processing element features car is set (large transport systems only). 23:16 dst_id 0x00 destination id: the destinationid (or least significant byte of the destination id if large transport system) associated with the error. 31:24 msb_dst_id 0x00 msb destination id: the most significant byte of the destinationid associated with the error. this field is valid only if bit 27 of the processing element fea- tures car is set (large transport systems only). table 39 logical/transport layer device id capture csr
82 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes logical/transport layer control capture csr this register contains error information. ltlcccsr is stored in each port and the message unit, although the values in this register can differ between each port and message uni t. the message unit ltlcccsr cannot lock if any port has locked; no port ltlcccsr can lock if the message unit or any other port has locked. undefined results will occur if this register is written while actual logical/trans port layer errors are being detected by the port. name: ltl_ctrl_cap_csr address: 0x00061c note: 1. the above register is described in the rio specification part 8, sec. 2.3.2.7 port-write target deviceid csr this register contains the target device id to be us ed when a device generates a maintenance port-write operation to report errors to a system host. name: port_wr_tid_csr address: 0x000628 note: 1. the above register is described in the rio specification part 8, sec. 2.3.2.8 port 0 error detect csr the port 0 error detect register indicates transmission erro rs that are detected by the hardware. software can write bits in this register with ?1? to cause the error rate counter to increment. undefined results will occur if this register is written while actual physical layer errors are being detected by the port. bit field name reset value comment 15:0 - 0 reserved. 23:16 msg_info 0x00 message information: letter, mbox, and message for the last message request received for the mailbox that had an error (message errors only). 27:24 trans_type 0x0 transaction type: transaction type associated with the error. 31:28 format_type 0x0 format type: format type associated with the error. table 40 logical/transport layer control capture csr bit field name reset value comment 14:0 - 0 reserved. 15 lrg_trans 1b0 large transport: deviceid size to use for a port-write 1b0 - use the small transport deviceid 1b1 - use the large transport deviceid. 23:16 dev_id 0x00 deviceid: this is the port-wr ite target deviceid. 31:24 dev_id_msb 0x00 deviceid msb: this is the most significant byte of the port-write target deviceid (large transport systems only). table 41 port-write target deviceid csr
83 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes name: p0_err_det_csr address: 0x000640 note: 1. the above register is described in the rio specification part 8, sec. 2.3.2.10 port 0 error rate enable csr this register contains the bits that c ontrol when an error condition is allowed to increment the error rate counter in the port 0 error rate threshold register and lock the port 0 error capture registers. name: p0_err_rate_en_csr address: 0x000644 bit field name reset value comment 0 link_tout 1b0 link time-out: an acknowledge or link-response control symbol is not received within the specified time-out interval. 1 uns_ctrl_sym 1b0 unsolicited acknowledge control symbol: an unexpected acknowledge control symbol was received. 2 delin_err 1b0 delineation error: received unaligned /sc/ or /pd/ or undefined code-group. 3 - 0 reserved. 4 proto_err 1b0 protocol error: an unexpected packet or control symbol was received. 5 nout_ackid 1b0 non-outstanding ackid: link-response received with an ackid that is not outstanding. 16:6 - 0 reserved. 17 rcv_pkt_exc 1b0 received packet exceeds 276 bytes: received packet which exceeds the maximum allowed size. 18 rcv_bad_crc 1b0 received packet with bad crc: received packet with a bad crc value. 19 rcv_pkt_uack 1b0 received packet with unexpected ackid: received packet with unexpected ackid value (out-of-sequence ackid). 20 rcv_pkt_nctrl 1b0 received packet-not-accepted control symbol: received packet-not-accepted acknowledge control symbol. 21 rcv_ack_sym 1b0 received acknowledge cont rol symbol with unexpected ackid: received acknowledge control symbol with unexpected ackid (packet-accepted or packet-retry). 22 rcv_cc_sym 1b0 received corrupt control symbol: received a control symbol with a bad crc value. 31:23 - 0 reserved. table 42 port 0 error detect csr bit field name reset value comment 0 link_tout_en 1b0 link time-out enable: enable error rate counting of link time-out errors. table 43 port 0 error rate enable csr
84 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes note: 1. the above register is described in the rio specification part 8, sec. 2.3.2.11 port 0 attribute capture csr the error capture attribute register indicates the type of in formation contained in the port n error capture registers. in the case of multiple detected errors during the same clock cy cle one of the errors must be reflected in the error type field. the error that is reflected is implementation dependent. undefined re sults will occur if this register is written while actual physical layer errors are being detected by the port. also, there could be latency between asserting an interrupt from output-degraded encountered or output-failed encountered to loadi ng this register, such that the interrupt is asserted a few cycles before the error is captured into this register. 1 uns_ack_sym_e n 1b0 unsolicited acknowledge control symbol enable: enable error rate counting of unsolicited acknowledge control sym- bol errors. 2 delin_err_en 1b0 delineation error enable: enable error rate counting of delineation errors. 3 - 0 reserved. 4 proto_err_en 1b0 protocol error enable: enable error rate counting of protocol errors. 5 nout_ackid_en 1b0 non-outstanding ackid enable: enable error rate counting of link-response received with an ackid that is not outstanding. 16:6 - 0 reserved. 17 rcv_pkt_exc_e n 1b0 received packet exceeds 276 bytes: enable error rate counting of packet which exceeds the maximum allowed size. 18 rcv_bad_crc_e n 1b0 received packet with bad crc enable: enable error rate counting of packet with a bad crc value. 19 rcv_pkt_ack_e n 1b0 received packet with unexpected ackid enable: enable error rate counting of packet with unexpected ackid value (out-of-sequence ackid). 20 rcv_pkt_sym_e n 1b0 received packet-not-accepted control symbol enable: enable error rate counting of received packet-not-accepted control symbols. 21 rcv_ack_sym_e n 1b0 received acknowledge control symbol with unexpected ackid enable: enable error rate counting of an acknowledge control symbol with an unexpected ackid. 22 rcv_cc_sym_en 1b0 received corrupt control symbol enable: enable error rate counting of a corrupt control symbol. 31:23 - 0 reserved. bit field name reset value comment table 43 port 0 error rate enable csr
85 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes name: p0_attr_cap_csr address: 0x000648 note: 1. the above register is described in the rio specification part 8, sec. 2.3.2.12 port 0 packet/control symbol capture 0 csr this register contains the first 4 bytes of captured packe t symbol information or a control character and control symbol. undefined results will occur if this register is written while actual physical layer errors are being detected by the port. als o, there could be latency between asserting an interrupt from output-degraded encountered or output-failed encountered to loading this register, such that the interrupt is asserted a few cycles before the error is captured into this register. name: p0_pkt_cap_0_csr address: 0x00064c note: 1. the above register is described in the rio specification part 8, sec. 2.3.2.13 bit field name reset value comment 0 cap_valid_info 1b0 capture valid info: this bit is set by hardware to indicate that the packet/control symbol capture registers contain valid information. for control symbols, only capture register 0 will contain meaningful information. 7:1 - 0 reserved. 23:8 ext_capt_info 0x0000 extended capture information[0:15]: eci contains the control/data c haracter signal corresponding to each byte of captured data. eci[0] = bit associated with p0psc0csr[0:7] eci[1] = bit associated with p0psc0csr[8:15] eci[2] = bit associated with p0psc0csr[16:23] eci[3] = bit associated with p0psc0csr[24:31] eci[4] = bit associated with p0psc1csr[0:7] eci[5] = bit associated with p0psc1csr[8:15] ... eci[14] = bit associated with p0psc3csr[16:23] eci[15] = bit associated with p0psc3csr[24:31] 28:24 err_type 0x0 error type: the encoded value of the bit in the port 0 error detect csr that describes the error captured in the port 0 error capture csrs. 29 - 0 reserved. 31:30 info_type 2b00 info type, type of information logged: 2b00 - packet 2b01 - control symbol (only erro r capture register 0 is valid) 2b10 - implementation specific 2b11 - undefined. table 44 port 0 attribute capture csr bit field name reset value comment 31:0 capt_0 all 0s capture 0: control character and control symbol or bytes 0 to 3 of packet header. table 45 port 0 packet/control symbol capture 0 csr
86 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes port 0 packet capture 1 csr error capture register 1 contains bytes 4 through 7 of the packet header. undefined results will occur if this register is written while actual physical layer errors are being detected by the port. also, there could be latency between asserting an interrupt from output-degraded encountered or output-failed en countered to loading this register, such that the interrupt is asserted a few cycles before the error is captured into this register. name: p0_pkt_cap_1_csr address: 0x000650 note: 1. the above register is described in the rio specification part 8, sec. 2.3.2.14 port 0 packet capture 2 csr error capture register 2 contains bytes 8 through 11 of the packet header. undefined results will occur if this register is written while actual physical layer errors are being detected by the port. also, there could be latency between asserting an interrupt from output-degraded encountered or output-failed en countered to loading this register, such that the interrupt is asserted a few cycles before the error is captured into this register name: p0_pkt_cap_2_csr address: 0x000654 note: 1. the above register is described in the rio specification part 8, sec. 2.3.2.15 port 0 packet capture 3 csr error capture register 3 contains bytes 12 through 15 of the packet header. undefined results will occur if this register is written while actual physical layer errors are being detected by the port. also, there could be latency between asserting an interrupt from output- degraded encountered or output-failed encountered to loading this register, such that the interrupt is asserted a few cycles before the error is captured into this register. name: p0_pkt_cap_3_csr address: 0x000658 note: 1. the above register is described in the rio specification part 8, sec. 2.3.2.16 bit field name reset value comment 31:0 capt_1 all 0s capture 1: control character and control symbol or bytes 4 to 7 of packet header. table 46 port 0 packet/control symbol capture 1 csr bit field name reset value comment 31:0 capt_2 all 0s capture 2: control character and control symbol or bytes 8 to 11 of packet header. table 47 port 0 packet/control symbol capture 2 csr bit field name reset value comment 31:0 capt_3 all 0s capture 3: control character and control symbol or bytes 12 to 15 of packet header. table 48 port 0 packet/control symbol capture 3 csr
87 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes port 0 error rate csr the port 0 error rate register is a 32-bit register used wi th the port 0 error rate threshold register to monitor and control the reporting of transmission errors. name: p0_err_rate_csr address: 0x000668 note: 1. the above register is described in the rio specification part 8, sec. 2.3.2.17 port 0 error rate threshold csr the port 0 error rate threshold register is a 32-bit register used to control the reporting of the link status to the system host. bit field name reset value comment 7:0 err_rate_cntr 0x00 error rate counter: these bits maintain a count of the number of transmission errors that have been detected by the port, decre mented by the error rate bias mechanism, to create an indication of the link error rate. software should not attempt to write this field to a value higher than failed threshold trigger plus the number of errors specified in the err field (the maximum erc value). 15:8 peak_err_rate 0x00 peak error rate: this field contains the peak value attained by the error rate counter. 17:16 err_rate_rec 2b00 error rate recovery: these bits limit the incrementing of the error rate counter above the failed threshold trigger: 2b00 - only count 2 errors above 2b01 - only count 4 errors above 2b10 - only count 16 errors above 2b11 - do not limit incrementing the error rate count note that the error rate counte r will never increment above 0cff, even if the combination of the settings of err and the failed thresh- old trigger might imply that it would. 23:18 - 0 reserved. 31:24 err_rate_bias 0x80 error rate bias: these bits provide the error rate bias value: 0x00 - do not decrement the error rate counter 0x01 - decrement every 1ms (+/-34%) 0x02 - decrement every 10ms (+/-34%) 0x04 - decrement every 100ms (+/-34%) 0x08 - decrement every 1s (+/-34%) 0x10 - decrement every 10s (+/-34%) 0x20 - decrement every 100s (+/-34%) 0x40 - decrement every 1000s (+/-34%) 0x80 - decrement every 10000s (+/-34%) other values are reserved and will cause undefined operation. table 49 port 0 error rate csr
88 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes name: p0_err_rate_csr address: 0x00066c note: 1. the above register is described in the rio specification part 8, sec. 2.3.2.18 8.2 configuration registers the configuration registers are grouped into functions with a maximum of 32 bits per register. every configuration register is assigned a reference number for ease of location. the reference number may be used as a pointer to the address of the register whenever the configuration address is being loaded or read. the registers are read or programmed as described in the programming section 6 of this datasheet. the registers are shown with bit 0 assigned as the lsb of the register and bit 31 assigned as the msb. flag register s are 64 bits long with bit 63 assigned as the msb. within the configuration registers there are five types of bi ts. the bit type is shown in the column labeled ?type?. the five types are: hw hard wired bits that are set by the hard wired configuration of the device. these cannot be changed by any programming method and are not affected by any of the resets. these bits may be read by any of the designated methods for reading configuration register s. these primarily deal with port structure and electrical connections. the s hadow is the external pin. rst bits that will enter a default mode based upon the hard-wired configuration during master reset. subsequently these bits may be changed by any of the designated programming methods, and then performing a ?load configuration? reset. these primar ily deal with internal device structure. these registers must have a shadow register. whenever a r egister containing rst bits are read by any of the designated reading methods, the actual content of the register is returned and not the content of the shadow register. rw bits that may be changed at any time without a load configuration reset. in the event jtag or i 2 c is used to alter the content, a load configuration reset must be performed. these primarily deal with data routing and flagging. these registers have no shadow, except for the jtag and i 2 c registers. these bits may be read by any of the designated methods. ro read only. upon a master reset or load configuration, these will go to a known state, but once initialized they are under control of the serb internally. srio transaction ids are an example of a register that the bit field name reset value comment 15:0 - 0 reserved. 23:16 err_deg_trig 0xff error rate degraded threshold trigger: these bits provide the threshold value for reporting an error condi- tion due to a degrading link. 0x00 - disable the error rate degraded threshold trigger 0x01 - set the error reporting threshold to 1 0x02 - set the error reporting threshold to 2 ... 0xff - set the error reporting threshold to 255. 31:24 err_fail_trig 0xff error rate failed threshold trigger: these bits provide the threshold value for reporting an error condi- tion due to a possibly broken link: 0x00 - disable the error rate failed threshold trigger 0x01 - set the error reporting threshold to 1 0x02 - set the error reporting threshold to 2 ... 0xff - set the error reporting threshold to 255. table 50 port 0 error rate threshold csr
89 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes interface must increment with each transaction, t he user may read the register, but the user cannot change the transaction ids without causing a sequence error. rc read to clear. these bits are associated with mbis t. contained within the mbist register is a bit to indicate bist is done. these bits will clear on read, only if mbist is complete. in addition, the configuration registers have a default mode. the defaults are shown in the column labeled ?reset value?. the reset values have the following form: hw the bit is set by the hard-wired pin configurat ion during reset. whether the user can subsequently change or not depends upon the type. protocols, port usage, etc. may affect the status of this bit. 0 bit defaults to zero 1 bit defaults to one x bit must be programmed before use. the initial state is not a concern. 8.2.1 reset and command register this register may be written in order to perform a reset and other functions. the bits automatically clear after performing the function, allowing the user to write again to per form an additional reset without having to clear the bits. the use of any of these bits will clear the memory and reset all state machines. the bits are listed in priority, with master reset overriding partial reset and partial reset overriding load configuration. name: rst_cmd_reg address: 0x18004 note: 1. see section 6.3 for a complete description and functionality of these resets. 2. partial reset must be used if the port configuration is changed. 3. does not reset plls and cannot be used if the port configuration was changed. 4. there is a master reset used by srio described in the rapidio part 4: physical layer 8/16 lp vlds specifi- cation. 8.2.2 serial port configuration register the serial port configuration register sets the speed of s-port. the serial port configuration register will default to the configuration designated on the hard-wired inputs upon mast er reset. once set, the register may be reconfigured as described. at any time, full read access is available from all indicated ports. bits field name type reset value comment 0 mr_rst rw 1b0 master reset: hard reset. the device will default to the hard wired configura- tion 1 pr_rst rw 1b0 partial reset: loads the shadow into the configuration registers and resets plls 2 ld_cfg rw 1b0 load configuration: loads the shadow into the configuration registers 31:3 - 0 reserved table 51 reset and command register
90 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes name: sport_cfg_reg address: 0x18008 8.2.3 parallel port configuration register the parallel port configuration register is used to set up the external qdrii sram memory. the default configuration is dependent upon the hard-wired inputs. a change to the contents of this register will also clear all memory contents in the queue. the registers may be read at any time, without upsetting the content. name: pport_cfg_reg address: 0x18010 note: 8.2.4 memory allocation register the memory allocation register is used to allocate both the internal and external memory to queue 0. internal memory is available for allocation in block size that are 1/8t h of the total sram capacity, hence 8 register bits[15:8]. the external memory allocation is dependent upon the size of the exter nal memory attached, but is available in block sizes that are 1/4th of the total external memory capacity and hence 4 register bits[7:4]. name: mem_alloc_reg address: 0x18014 note: bits field name type reset value comment 1:0 sp_speed rst hw s-port speed select: 00 = 1.25g, 01 = 2.5g, 10 = 3.125g, 11 = reserved 11:2 - 0 reserved 12 816_rio_destid rst hw 8 or 16 bit srio destination id: 0 = 8-bit destination id, 1 = 16-bit destination id 31:13 - 0 reserved table 52 serial port configuration register bit field name type reset value comment 0 pport_on rst hw parallel port on/off: 0 = on, 1 = off 1 - 0 reserved for future use 3:2 ext_mem_sz hw hw external memory size: 00 = 36m, 01 = 72m, 1x = reserved 31:4 - 0 reserved table 53 p-port configuration register bit field name type reset value comment 3:0 - 4h0 reserved 7:4 ext_mem_blk rw 4h0 external memory block allocation 15:8 int_mem_blk rw 8hff internal memory block allocation 31:16 - 0 reserved table 54 memory allocation register
91 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes 8.2.5 lost packet replacement register name: lost_pkt_rep_reg address: 0x18030 note: 0) if a single packet is lost, it will be replaced by a dummy packet to avoid breaking the memory addresses. if more than one packet is lost, an error will be generated instead of replacing. if this bit is set to 0, the lost packet is ignored. 8.2.6 source and destination ids the srio source and destination ids must be programmed to access the queue. these registers are read/write from any of the access ports. srio may program these registers using the overall device destination id, since direct srio access to the queue may otherwise not be available. in ad dition, a queue input or output may be programmed with either an 8 or 16 bit destination id. name : src_dest_id_reg address: 0x18034 note: 7:0) this is the queue source id for srio protocol. 15:8) this is the 16 bit extension for srio. these bits will be compared if the queue input is enabled for 16 bits. 23:16) this is the queue destination id for srio. 31:24) this is the 16 bit extension for srio on the destination id. these bits will be appended to the srio header if the queue output is enabled for 16 bits. 8.2.7 program almost empty / almost full register the pae and paf flags are each eight bits long for each of the queues. the eight bits allow the flags to be placed anywhere with an accuracy of 1/256 th of the total queue size. since the queue size is programmable, paf and pae are proportional indications and not accurate size counts. the pa e flag is the distance from empty and the paf flag is the distance from full. both may be placed anywhere in the memory, but cannot overlap to where paf + pae > 0ffh. these registers may be read or written from any of the sources. bit field name type reset value comment 0 rep_lost_pkt rw 1b0 queue 0 replace lost packets: 0 = no, 1 = yes 31:1 - 0 reserved table 55 lost packet replacement register bit field name type reset value comment 7:0 src_id_8 rw 8h0 source id is 8 bits: defaults to base queue number 15:8 src_id_16 rw 8h0 source id is 16 bits: defaults to zero 23:16 dest_id_8 rw 8h0 destination id is 8 bits: defaults to base queue number 31:24 dest_id_16 rw 8h0 destination id is 16 bits: defaults to zero table 56 source and destination id register
92 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes name: pae_paf_reg address: 0x18058 8.2.8 waterlevel control registers there is a waterlevel associated with each queue. if the wate rlevel is used, the watermark should be set to zero. if the queue is a doorbell master, the watermark should be set at maximum. watermark register name: water_mark_ reg address: 0x18068 waterlevel register name: water_level_ reg address: 0x1806c space available register name: space_ avail_reg address: 0x18070 bit field name type reset value comment 7:0 pae_q0 rw 8h0f program almost empty 15:8 paf_q0 rw 8h0f program almost full 31:16 - 16h0f0f reserved table 57 pae / paf register bit field name type reset value comment 22:0 water_mark rw 23h0 watermark: waterlevel trigger point 23 dw_pkt_cnt rw 1b0 d-word or packet count: 0 = count packets, 1 = count d-words 31:24 - 0 reserved table 58 watermark register bit field name type reset value comment 22:0 water_level ro 23h0 waterlevel: quantity in queue, in d-words or packets 31:23 - 0 reserved table 59 waterlevel register bit field name type reset value comment 22:0 spc_avail ro 23h0 space available: remaining space in d-words, will update to available space on next few clock cycles 31:23 - 0 reserved table 60 space available register
93 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes note: 1. the watermark is the trigger point at which the flag will be set. as a master that will always transmit new data as soon as it has arrived and been accepted, the watermark should be set to zero. 2. d-word or packet count indicates whether the watermark and waterlevel are in terms of packet count or in d- word count. 3. flush or single packet determines what happens when data is sent out of the queue. a. on flush, all data in the queue is transmitted, e xcept for new data that arrives during the flush. b. on single packet, only enough data is sent to lower the waterlevel below the watermark. presumably, in most situations, this will be a single packet or d-word. c. it should be noted that the flush or single packet works with the master/slave selection in the serial port configuration register . if the queue is a master, the waterlevel triggers the data transmission. if a slave, the waterlevel triggers a flag only and the queue may then be read. 8.2.9 mbist control register the mbist is the primary method for memory testing. the mb ist register is one of the few configuration registers with clear on read on most bits. it is expected that all bist will be controlled by one location/port, preventing conflicts that may develop from interacting ports, making t he clear on read a valid operational mode. name: config_reg_mbist address: 0x180c8 note: 1. mbist will start when bit 1 is 1, and bit 0 changes from 0 to 1. bit 1 will stay at "1" till mbist is done (bit 24 becomes 1), after that, bit 1 will be self cleared to 0. 8.2.10 qbist control register the qbist accompanies the mbist register. most bits are clear on read. bit field name type reset value comment 0 mbist_start rw 1b0 memory bist start: this bit self clears after mbist is complete 1 mbist_en rw 1b0 memory bist enable: this bit is read/write, must stay high during mbist 2 i2c_mem_en rw 1b0 i 2 c memory access enable: bits 1 and 2 are xor 7:3 - 0 reserved 15:8 mbist_mem_err rt 8h0 memory bist main memory block error: block 7 - 0 20:16 - 0 reserved 21 mb_p1_sr_me rt 1b0 memory bist port 1 / srio memory error 22 mb_p2_pp_me rt 1b0 memory bist port 2 / parallel port memory error 23 - 0 reserved 24 mb_done rt 1b0 memory bist done: if this bit is not ?1?, the flags from 8 -25 will not clear on read 25 mb_pass rt 1b1 memory bist pass this bit is meaningful only when bit 24 = 1 31:26 - 0 reserved table 61 mbist control register
94 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes name: config_reg_qbist address: 0x180cc note: qbist will start once qbist enable changes from 0 to 1 and stop when qbist enable changes from1 to 0. 2:1) bits 1 and 2 are exclusive of each other. 23:8) the error counter will wrap around once saturated. the user may check this counter against a timer to determine the bit error rate. 8.2.11 jtag device id register jtag device identification register is provided for use with identifying the device. the content is duplicated here to allow access from all available access ports. name: jtag_device_id address: 0x180d0 8.2.12 case scenario configuration registers case scenarios are used to generate srio outgoing packet headers when the serb initiates a packet. in the case of response packets, the incoming packet is used instead. a complete description is provided in the case scenario section. these registers are read/write from any of the access ports. the default values are functionally don?t care, since they cannot be used until programmed. bit field name type reset value comment 0 - 0 reserved 1 qbist_en rw 1b0 qbist enable; this bit is r/w and must stay high during qbist. changing from 0 to 1 will reset bits 23:8 and 25. 2 i2c_mem_en rw 1b0 i 2 c memory access enable; bits 1 and 2 are xor 7:3 - 0 reserved 23:8 qbist_err_cnt rc 16h0 qbist error counter block 7 - 0 24 - 0 reserved 25 qbist_pass rc 1b1 qdr memory bist pass 31:26 - 0 reserved table 62 qbist control register bit field name type reset value comment 0 stdrd_bit hw 0b1 standard bit: standard bit[0] = 1 per ieee-2001. 11:1 idt_jtag_id hw 0x033 idt jtag identification: jtag vendor id for idt. 27:12 idt_part_num hw 0x04f0 idt jtag part number: jtag device id for serb. 0x4f0 - srio / 18meg 0x4f1 - srio / 9meg 31:28 idt_ver_num hw 0x0 idt version number: version number of serb = 0. table 63 jtag device id register
95 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes case scenario packet header register name: cs0_pkt_header address: 0x18400 note: 1:0) priority - the priority for the srio packet header. cr is set to zero and ignored as part of the priority. default priority should be 00h, low priority. 3:2) tt - the srio transaction type. if set to 00h, the tr ansaction is 8 bits, if set to 01h, the transaction is 16 bits. other tt values are invalid. 7:4) ftype - defined in the srio specification, part 1, section 4.1. the only ftypes supported are types 5 (write) and 6 (swrite). 15:8) target address - the destination id for the packet to be sent. this byte will be included in all packets using this case scenario. 23:16) target address, x16 - the msb of the address if the srio transaction is 16 bits. if tt = 00, the target address msbs are used. 27:24) ttype - the sub transaction to the ftype defined in the same location as ftype. if ftype is 5 the only ttypes supported are nwrite and nwrite_r. size: the size is set by the hardware and should not be part of the case scenario. see srio spec., section 4.1.2. case scenario start address register the starting address for memory writes when performing swrite and nwrite operations with this case scenario. the address contained in the packet will increment appropriately starting from this location. upon a wrap or reset, the address will return to this value. name: cs0_strt_addr address: 0x18404 case scenario next address register bit field name type reset value comment 1:0 priority rw 2b0 srio priority packet 3:2 tt rw 2b0 transaction type, 00 = 8 bit, 01 = 16 bit 7:4 ftype rw 4h0 srio transaction format type 15:8 targetaddr rw 4h0 destination id for the transmission 23:16 targetaddr16 rw 8h0 extension for 16 bit if tt = 01; see note 1 27:24 ttype rw 4h0 transaction type (sub group of ftype) 31:28 - 0 reserved table 64 case scenario packet header register bit field name type reset value comment 30:0 strt_addr rw 31h0 start address: starting memory address for srio 31 - 0 reserved table 65 case scenario start address register
96 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes the current value for the address. whenever a new case sc enario is programmed, this value will be set to be iden- tical to the start address. the address will increment by the quantity of data transmitted with every packet. the next address will not rise beyond the stop address. if the wrap or stop bit in the following register is set to wrap, the next address will reset to the start address whenever stop address has been hit. if the wrap occurs in the middle of the packet, the next address will increment after the reset to indicate how much of the tail of the packet was written after the wrap. name: cs0_next_addr address: 0x18408 case scenario stop address register the final incremental address for writing. the higher addr ess may be included in the srio packet header, but in some cases the packet length may cause a write to an address higher than this value, in case of an overflow. the start address and stop address should be identical if the user does not want the address issued in the packet header to increment. name: cs0_stop_addr address: 0x1840c case scenario frame register name: cs0_frame_reg address: 0x18410 bit field name type reset value comment 30:0 next_addr rw 31h0 next address: current memory address for srio 31 - 0 reserved table 66 case scenario next address register bit field name type reset value comment 30:0 stop_addr rw 31h0 stop address: maximum memory address for srio 31 - 0 reserved table 67 case scenario stop address register bit field name type reset value comment 9:0 frame_size rw 10h0 frame size 14:10 frame_offset rw 5h0 frame offset: offset on first count 15 tally_flag rw 1b0 set tally flag: 1 = send doorbell to dest id on count = size 23:16 frame_count rw 8h0 frame count: counts frame, reset on doorbell 27:24 - 0 reserved 28 mem_wrap_stp rw 1b0 memory wrap or stop: stop or wrap on stop address table 68 case scenario frame register
97 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes note: 9:0) frame size - the maximum frame size of the data for the ti application. whenever the frame size has been hit, a doorbell will be issued to wake up the dsp (if doorbell is enabled). 14:10) frame offset - ti requested that we have an offset to the first frame size to allow them to compensate for delays through the system. 15) doorbell - this bit indicates that the frame size is active and the doorbell should be sent when frame size is hit. 23:16) frame count - the location for the current value of the counter for frame size. when the count reaches frame size and the doorbell is active, the doorbell will be sent and frame count will reset to zero. 27:24) lite dest id - lite protocols have only four bits to select either a destination id or case scenario. to solve the problem of what happens when a lite protocol selects a case scenario and then the packet needs to be loaded into a queue, the lite dest id is placed in the case scenario. the queue inputs may be programmed to allow selection of multiple queues with the same destination id. 28) memory wrap or stop - defines whether the next address will wrap or stop when it hits stop address. 0 = wrap, 1 = stop. 29) memory doorbell - indicates whether a doorbell should be sent when the next address hits the stop address. 31:30) frame size plus offset should not exceed ten bits. 8.2.13 missing packet detection registers missing packet detection mechanism consists of memory st art address, current memory address, memory address increment and memory stop address registers and are full y described in the section on missing packet detection and replacement. memory start address register name: mem_strt_addr address: 0x18580 current memory address register 29 flag_wrap_stp rw 1b0 set flag on wrap or stop: used with either stop or wrap 31:30 frame_cnt ro 2b0 the highest two bits of the frame count bit field name type reset value comment 30:0 mem_strt_addr rw 31h0 memory start address: start address for missing packet detection 31 - 0 reserved table 69 missing packet start address register bit field name type reset value comment table 68 case scenario frame register
98 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes name: cnt_mem_addr address: 0x18584 memory address increment register name: mem_addr_mem address: 0x18588 memory stop address register name: mem_stop_addr address: 0x1858c note: 1. the stop address must align with the start address and the address increment. a misalignment may cause the stop address to be missed. 8.2.14 packet interval timer register the pps has no storage capability and cannot accept packets faster that its processing capability. to solve this problem, both the data packets and the doorbells exiting s-port 1 may be timed with a programmable interval timer. the interval timer uses the phy clock 156.25mhz as the tick. a se t interval is programmed into the pps packet interval timer register. when a packet is sent using srio out s-port 1, the interval timer will begin counting down, starting when the packet has completed. when the counter reaches zero, a following packet may be sent. the pps acceptance of doorbells is much faster than data packets: therefore, they will be accomplished by a second counter with the countdown initiated when the doorbell starts. data packet interval timer register bit field name type reset value comment 30:0 cnt_mem_addr rw 31h0 current memory address: used to hold the current memory address 31 - 0 reserved table 70 missing packet current address register bit field name type reset value comment 5:0 mem_addr_inc rw 6h0 memory address increment: used to predict next current memory address 31:6 - 0 reserved table 71 missing packet address increment register bit field name type reset value comment 30:0 mem_stop_addr rw 31h0 memory stop address: the last allowed memory address 31 - 0 reserved table 72 missing packet stop address register
99 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes name: data_ itv_time address: 0x185c0 doorbell packet interval timer register name: db_itv_ time address: 0x185c4 8.2.15 missing packet size register this register is used to set the size of missing/replacement packet payload. name: miss_pkt_sz address: 0x185cc 8.2.16 missing packet address logging register 1 upon the detection of a missing packet, the address of the next valid packet will be loaded into this register. the user may then poll this register to identify the address. name: miss_pkt_log_1 address: 0x19d60 note: 30:0) the address of the next valid packet following a mi ssing packet is loaded into this register whenever the missing packet flag is toggled. when either the missi ng packet flag register is read and cleared, this register will also clear. bit field name type reset value comment 15:0 data_pkt_time rw 16h0 data packet timer: counts down, holds at 00h 31:16 - 0 reserved table 73 data packet interval timer register bit field name type reset value comment 15:0 dbell_pkt_time rw 16h0 doorbell packet timer: counts down, holds at 00h 31:16 - 0 reserved table 74 doorbell packet interval timer register bit field name type reset value comment 5:0 miss_pkt_sz rw 6h0 missing packet size: size for inserted packet payload 31:6 - 0 reserved table 75 missing packet size registers bit field name type reset value comment 30:0 mis_pkt_log_1 note 31h0 missing packet address log: the address of the first valid packet following a missing packet 31 - 0 reserved table 76 missing packet address logging register
100 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes 8.2.17 missing packet address logging register 2 this register is identical to the missing packet address logging register , except it is associated with the ? missing packet programmable flag register ? instead of the ? missing packet flag register ?. name: miss_pkt_log_2 address: 0x19f20 note: 30:0) the address of the next valid packet following a mi ssing packet is loaded into this register whenever the missing packet flag is toggled. when either the missi ng packet flag register is read and cleared, this register will also clear. 8.3 serb error counter registers 8.3.1 s-port data packet received counter as part of the device error management, there is a data packet received counter associated with s-port. this counter is reset by reading. the counter will count every data packet entering the port. upon reaching full count, the packets will remain at full count and will not wrap. name: data_pkt_rcv_cnt address: 0x185dc 8.3.2 s-port data packet transmitted counter as part of the device error management, there is a data packet transmitted counter associated with s-port. this counter is reset by reading. the counter will count every data packet leaving the port. upon reaching full count, the packets will remain at full count and will not wrap. name: data_pkt_xmt_cnt address: 0x185e0 8.3.3 s-port priority packet received counter as part of the device error management, there is a priority packet received counter associated with s-port. this counter is reset by reading. the counter will count every priority packet entering the port. upon reaching full count, the packets will remain at full count and will not wrap. bit field name type reset value comment 30:0 mis_pkt_log_2 note 31h0 missing packet address log for ti dsp: the address of the first valid packet following a missing packet 31 - 0 reserved table 77 missing packet address logging register for ti dsp bit field name type reset value comment 31:0 sdp_rx_cnt rw 32h0 s-port data packet received counter: reset 0 by reading table 78 s-port data packet received counter bit field name type reset value comment 31:0 sdp_tx_cnt rw 32h0 s-port data packet transmitted counter: reset 0 by reading table 79 s-port data packet transmitted counter
101 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes name: prio_pkt_rcv_cnt address: 0x185e4 note: 1. single 32-bit aggregate counter to count all the non- blocking (config write request and config read request) and blocking (srio nread and doorbell request frame and lite read) priority packets being received on port 1 interface. 8.3.4 s-port priority packet transmitted counter as part of the device error management, there is a priority packet transmitted counter associated with s-port. this counter is reset by reading. the counter will count every priority packet leaving the port. upon reaching full count, the packets will remain at full count and will not wrap. name: prio_pkt_xmt_cnt address: 0x185e8 note: 1. single 32-bit aggregate counter to count all the prio rity packets (doorbell request, nwrite response, config read response, config write response and doorbell response) being transmitted on port 1 interface. 8.3.5 s-port packet received counters as part of the device error management, there is a packet received counter associated with the queue. these counters are reset by reading. each counter will count every packet entering the queue. upon reaching full count, the packets will remain at full count and will not wrap. name: sp_pkt_rcv_cnt address: 0x185ec 8.3.6 s-port packet transmitted counters as part of the device error management, there is a packet transmitted counter associated with the queue. these counters are reset by reading. each counter will count ever y packet sent from the queue. upon reaching full count, the packets will remain at full count and will not wrap. bit field name type reset value comment 31:0 spp_rx_cnt rw 32h0 s-port priority packet received counter: reset 0 by reading table 80 s-port priority packet received counter bit field name type reset value comment 31:0 spp_tx_cnt rw 32h0 s-port priority packet transmitted counter: reset 0 by reading table 81 s-port priority packet transmitted counter bit field name type reset value comment 31:0 spkt_rcv_cnt rw 32h0 s-port packet received counter: reset 0 by reading table 82 s-port packet received counter
102 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes name: sp_pkt_xmt_cnt address: 0x1860c 8.4 serdes quad control register the srio specification has defined registers for use in conf iguring and controlling the 1x/4x quad serdes srio port (s- port 1 on the serb). the serb shall utilize the standard r egister and observe standard 1x/4x configuration protocols. for the rest of the serial ports definition, refer to ?rapi dio interconnect specification part vi: physical layer 1x/4x lp- serial specification. name: serdes_quad_ctrl address: 0x18c30 8.5 flag and flag mask registers the flag registers are 32-bit registers and include an additional 32- bit register for the flag masks. each register contains a maximum of 8 flags plus the masks and destination ids associ ated with those flags. the typical flag register content is shown below table. the flags within a register are select ed to generate same interrupt or generate doorbells destined for the same location. the interrupting flag may individually be ident ified by the register contents that may be read or sent with a doorbell. contained within each flag register is a series of four ma sk registers for the flags. the flag mask registers are used to create doorbells and interrupts. this means there are five register locations associated with each flag. the content of each flag register is available for r eading at any time by any of the following methods: srio commands i 2 c interface jtag bit field name type reset value comment 31:0 spkt_xmt_cnt rw 32h0 s-port packet transmitted counter: reset 0 by reading table 83 s-port packet transmitted counter bit field name type reset value comment 1:0 - 0 reserved 4:2 tcoeff[2:0] rw 3b0 transmi t pre-emphasis control: 000 = 0% emphasis 001 = 6.5% emphasis 010 = 13% emphasis 011 = 19.5% emphasis 100 = 26% emphasis 101 = 32.5% emphasis 110 = 39% emphasis 111 = 45.5% emphasis 6:5 - 0 reserved 9:7 txdrvsel rw 3b010 tx drive strength select 000 = maximum drive strength 010 = srio long haul 100 = srio short haul 111 = minimum drive strength 31:10 - 0 reserved table 84 serdes quad control register
103 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes note: 7:0) these 8 bits within the register are where the fl ags are stored. as noted below, there is a name, a status for the flag and a description of the flag shown for each flag. some flags are updated real time, while others latch and must be cleared. 8) designates whether source and destination ids of the doorbell should use 8 bits or 16 bits. the true tt is two bits, but only one bit is required to make 8/16 designation. 9) wr32 designates whether a write to this register is 8 bits or 32 bits. an 8 bit write would write a mask to the flag portion of the register to clear the masked fl ags. within the mask, any flag that is overwritten by ?1? would be cleared. any flag overwritten with a ?0? woul d be unaffected by the write. a 32 bit write to this register would be required to alter t he destination id and tt portions of the register. in a 32 bit write, the flags could be cleared or left unaffected, based upon the state of the 8 lsbs of the write, the same as with the 8 bit write. note that rt flags cannot be cleared. 11:10) these bits indicate the priority t hat should be used for any srio doorbell packet. 15:12) any unused bits are indicated as reserved. 23:16) this is the 8 bit destination id for a doorbell on s- port if the mask bits 8-15 allow a doorbell to be created. 31:24) this is the 16 bit extension to the destinati on id for doorbells on s-port if using srio extended addresses. 39:32) these are the mask bits for the flags. any unmasked flag will cause a doorbell to be sent on s-port. 47:40) reserved for future use. 55:48) this is the mask for the int 0 interrupt pin. 63:56) this is the mask for the int 1 interrupt pin. 8.5.1 key to the flag registers the flag registers are listed in the order of priority for doorbells and interrupts. all masks power up and reset to fully masked and are enabled by unmasking the bits. all flag register tables are shown with the following column headings and symbols within the register: #: the bit location within the designated register signal: an abbreviated name for the flag stat: indicates whether the flag may be cleared ? cl: clearable flag. these flags will latch upon toggli ng and must be cleared by a write to the register ? rt: indicates the flag is a real time and always repr esents current conditions. clearing a rt flag is not possible rw: used with masks to indicate the bits are read/write through a configuration read/write # signal stat description 7-0 flags x there are up to 8 flags contained in the register 8 tt rw defines whether the srio doorbell is an 8 or 16 bit destination id 9 wr32 rw 0 = write 8 bits (clear flags only), 1 = write 32 bits (write new dest ids) 11-10 prio rw priority for doorbell packet 15-12 res x unused bits 23-16 destid rw destination id for srio doorbell 31-24 destid rw destination id for srio doorbell, for 16 bit extension 39-32 mask rw s-port doorbell mask 47-40 res x unused bits 55-48 mask rw interrupt 0 mask 63-56 mask rw interrupt 1 mask table 85 flag and flag mask register
104 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes 8.5.2 srio link status the rapidio ?error management extensions specification? requi res specific configuration status registers at desig- nated addresses. these csrs are described in section 2 of the identified spec, and shoul d be referenced for more specific information. 8.5.3 s-port link status the flags of the ?s-port link status?. th is flag register is used to identify error that is not covered by the srio error management extensions specification. name: sp_lnk_stat_flag address: 0x19c04 sp_lnk_stat_mask 0x19cc4 this register cannot generate an srio packet. note: 4) indicates that in response to a previously sent doorbell a ?retry? indication was received. 8.5.4 device configuration error these flags are generated whenever a confi guration error occurs. when a configuration error occurs the serb will not function, however these flags may be masked to create doorbel ls and interrupts on the ports designated by the masks. all of these flags are real time (rt) and cannot be clear ed except by re-configuring the offending register. name: config_err_flag address: 0x19c0c config_err_mask 0x19ccc if this register generates an srio packet, the packet will be a doorbell. # signal stat description 3:0 - reserved 4 retry cl srio doorbell response with retry received 5 jtag cl jtag error 6 eme cl srio error management extension interrupt 7 - unused bit 8 tt rw defines whether the srio doorbell is an 8 or 16 bit destination id 9 wr32 rw 0 = write 8 bits (clear flags only), 1 = write 32 bits (write new dest ids) 11-10 prio rw priority for doorbell packet 15-12 - unused bits 23-16 destid rw destination id for srio doorbell 31-24 destid rw destination id for srio doorbell, for 16 bit extension 39-32 mask rw s-port doorbell mask 47-40 - unused bits 55-48 mask rw interrupt 0 mask 63-56 mask rw interrupt 1 mask table 86 s-port 1 link status for lite register # signal stat description 0 err rt external memory is allocated but not available table 87 device configuration error register
105 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes note: 0) error - this flag indicates that the serb is progra mmed to have more memory than is actually attached to p-port. 8.5.5 srio dma status register these flags are generated whenever an srio error occurs that is not covered by one of the error flags defined in the srio specification. these errors are monitored by the case scenarios, so there is one flag register per case scenario. name: cs0_dma_stat_flag address: 0x19c10 cs0_dma_stat_mask 0x19cd0 if this register generates an srio packet, the packet will be a doorbell. 7-1 - reserved 8 tt rw defines whether the srio doorbell is an 8 or 16 bit destination id 9 wr32 rw 0 = write 8 bits (clear flags only), 1 = write 32 bits (write new dest ids) 11-10 prio rw priority for doorbell packet 15-12 - unused bits 23-16 destid rw destination id for srio doorbell 31-24 destid rw destination id for srio doorbell, for 16 bit extension 39-32 mask rw s-port doorbell mask 47-40 - unused bits 55-48 mask rw interrupt 0 mask 63-56 mask rw interrupt 1 mask # signal stat description 0 memstop rt srio next address has reached stop address 1 tally1 rt the packet tally counter wrapped on s-port 7-2 - reserved 8 tt rw defines whether the srio doorbell is an 8 or 16 bit destination id 9 wr32 rw 0 = write 8 bits (clear flags only), 1 = write 32 bits (write new dest ids) 11-10 prio rw priority for doorbell packet 15-12 - unused bits 23-16 destid rw destination id for srio doorbell 31-24 destid rw destination id for srio doorbell, for 16 bit extension 39-32 mask rw s-port doorbell mask 47-40 - unused bits 55-48 mask rw interrupt 0 mask 63-56 mask rw interrupt 1 mask table 88 srio dma status register # signal stat description table 87 device configuration error register
106 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes note: 0) memory stop - the srio memory address has incremented to or beyond the stop address. this flag may be used to send a doorbell if the address reaches the stop address (triggering the flag condition), the flag will remain active until software writes a ?1? to clear the flag. 1) tally1 - the packet tally counter will wrap. if the user whishes to know it wrapped, the flag may be used. 8.5.6 missing 2 packet flag register if missing 2 packet is turned on and two or more packets are missi ng, the flags of this register will be used. note that if this register is read and cleared, the ?missing packe t address logging register 1? will also be cleared. name: miss2_pkt_flag address: 0x19c50 miss2_pkt_mask 0x19d10 if this register generates an srio packet, the packet will be a doorbell. note: 0) missing 2 - if two or more packets are missing, t hey cannot be replaced. this flag indicates that a catastrophic error has occurred in the pps application. 8.5.7 fifo empty flag register if this register generates an srio packet, the packet will be a doorbell. name: fifo_empty_flag address: 0x19c60 fifo_empty_mask 0x19d20 # signal stat description 0 missin2 cl two or more srio packets were detected as missing 7-1 - reserved 8 tt rw defines whether the srio doorbell is an 8 or 16 bit destination id 9 wr32 rw 0 = write 8 bits (clear flags only), 1 = write 32 bits (write new dest ids) 11-10 prio rw priority for doorbell packet 15-12 - unused bits 23-16 destid rw destination id for srio doorbell 31-24 destid rw destination id for srio doorbell, for 16 bit extension 39-32 mask rw s-port doorbell mask 47-40 - unused bits 55-48 mask rw interrupt 0 mask 63-56 mask rw interrupt 1 mask table 89 missing packet flag register # signal stat description 0 ef rt queue 0, empty flag 1 pae rt queue 0, programmable almost empty 2 pr rt queue 0, packet ready 3 w rt queue 0, waterlevel exceeds packet count 7-4 - reserved table 90 fifo queue empty flag register
107 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes note: 0) ef = no data remains in queue 1) pae = programmable on 1/256 th portions of queue memory 2) pr = full packet ready for reading, reading one byte or more will kill flag 3) w = waterlevel is at or past the watermark (either byte or packet count) 7-4) res = reserved bit 8.5.8 fifo full flag register if this register generates an srio packet, the packet will be a doorbell. name: fifo_full_flag address: 0x19c64 fifo_full_mask 0x19d24 8 tt rw defines whether the srio doorbell is an 8 or 16 bit destination id 9 wr32 rw 0 = write 8 bits (clear flags only), 1 = write 32 bits (write new dest ids) 11-10 prio rw priority for doorbell packet 15-12 - unused bits 23-16 destid rw destination id for srio doorbell 31-24 destid rw destination id for srio doorbell, for 16 bit extension 39-32 mask rw s-port doorbell mask 47-40 - unused bits 55-48 mask rw interrupt 0 mask 63-56 mask rw interrupt 1 mask # signal stat description 0 ff rt queue 0, full flag, incoming packet rejected 1 paf rt queue 0, programmable almost full 2 sa rt queue 0, one or more max sized packet space available 7-3 - reserved 8 tt rw defines whether the srio doorbell is an 8 or 16 bit destination id 9 wr32 rw 0 = write 8 bits (clear flags only), 1 = write 32 bits (write new dest ids) 11-10 prio rw priority for doorbell packet 15-12 - unused bits 23-16 destid rw destination id for srio doorbell 31-24 destid rw destination id for srio doorbell, for 16 bit extension 39-32 mask rw s-port 1 doorbell mask 47-40 - unused bits 55-48 mask rw interrupt 0 mask 63-56 mask rw interrupt 1 mask table 91 fifo queue full flag register # signal stat description table 90 fifo queue empty flag register
108 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes note: 0) ff = no space remains in queue, the entire incoming packet was rejected 1) paf = programmable on 1/256 th portions of queue memory 2) sa = space available for one full sized packet. a doorbell will be sent whenever the flag changes state. flag is inactive whenever the incoming packet may prevent an additional packet entering. 8.5.9 dsp interrupt flag register in the ti application, if a doorbell is sent to the dsp, it must have a programmable content. to solve the problem, unmasked flags may send a doorbell to the dsp upon toggli ng. when enabled, every unmasked flag (except the packet tally flags) will send a doorbell with the programmed content to the dsp at the programmed destination id. this register sends an srio doorbell on s-port and is not c apable of generating an interrupt on int 0 or int 1. since it has programmable content, there is no register number associated with this register. name: dsp_int_flag address: 0x19ca0 dsp_int_mask 0x19e60 if this register generates an srio packet, the packet will be a doorbell. note: 0) this flag will toggle if any other unmasked flag toggles. this flag may be cleared only by clearing the source flag. 24:16) this is the destination id for the dsp that must receive the programmed doorbell. this may be any destination. 39:32) the doorbell is turned on and off by masking bit 0. th is mask does not affect the source flags. the source flags each have their own flags and masks. the int 1 ma sk associated with each individual flag is used to enable the flags to toggle the dsp interrupt flag. the tally flag should always be masked off in int 1 masks on the individual flag registers to avoid toggl ing the dsp interrupt flag. int 1 and the dsp mask share a mask and must toggle due to the same flags. 63:48) the content of the doorbell is a 16 bit user programmable pointer. 8.5.10 tally doorbell flag register if the "tally 1" flag in the srio dma status information regist er toggles in the ti application, the user may wish to send a doorbell to the dsp. the content of the doorbell is user progra mmable, to allow the user to select an interrupt within the dsp. this doorbell does not interfere with any doorbells or interrupts generated by the srio dma status information register. # signal stat description 0 flag rt the aggregate of all unmasked flags 7-1 - reserved 8 tt rw defines whether the srio doorbell is an 8 or 16 bit destination id 9 wr32 rw 0 = write 8 bits (clear flags only), 1 = write 32 bits (write new dest ids) 11-10 prio rw priority for doorbell packet 15-12 - unused bits 23-16 destid rw destination id for srio doorbell 31-24 destid rw destination id for srio doorbell, for 16 bit extension 39-32 mask rw s-port doorbell mask 47-40 - unused bits 63-48 pointer rw programmable doorbell contents table 92 dsp interrupt flag register
109 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes this register sends an srio doorbell on s-port and is not c apable of generating an interrupt on int 0 or int 1, therefore there is no register number. name: cs0_taly_dbel_flag address: 0x19e10 cs0_taly_dbel_mask 0x19ed0 if this register generates an srio packet, the packet will be a doorbell. note: 1) this flag is identical to the flag in t he "srio dma status information" register. 24:16) this is the destination id for the dsp that must re ceive the tally indication doorbell. it is not required that this be the same destination as in the "srio dma status information" register. 39:32) the doorbell is turned on and off by masking bit 1. 63:48) the content of the doorbell is a 16 bit user programmable pointer. 8.5.11 missing 2 packet programmable flag register if missing 2 packet is turned on and two or more packets are missing, this register will allow a programmable doorbell to be sent to a designated srio destination id. note that if th is register is read and cleared, the ?missing packet address logging register 2? will also be cleared. name: miss2_pgrm_flag address: 0x19e50 miss2_pgrm_mask 0x19f10 if this register generates an srio packet, the packet will be a doorbell. # signal stat description 0- reserved 1 tally1 cl the packet tally counter wrapped on s-port 7-2 - unused bits 8 tt rw defines whether the srio doorbell is an 8 or 16 bit destination id 9 wr32 rw 0 = write 8 bits (clear flags only), 1 = write 32 bits (write new dest ids) 11-10 prio rw priority for doorbell packet 15-12 - unused bits 23-16 destid rw destination id for srio doorbell 31-24 destid rw destination id for srio doorbell, for 16 bit extension 39-32 mask rw s-port doorbell mask 47-40 - unused bits 63-48 pointer rw programmable doorbell contents table 93 tally doorbell flag register # signal stat description 0 missin2 cl two or more srio packets were detected as missing 7-1 - reserved 8 tt rw defines whether the srio doorbell is an 8 or 16 bit destination id 9 wr32 rw 0 = write 8 bits (clear flags only), 1 = write 32 bits (write new dest ids) 11-10 prio rw priority for doorbell packet table 94 missing packet programmable flag register
110 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes note: 0) missing 2 - if two or more packets are missing, t hey cannot be replaced. this flag indicates that a catastrophic error has occurred in the pps application. the programmable contents of locations 63-48 will be sent to the destination id in locations 31-16. 15-12 - unused bits 23-16 destid rw destination id for srio doorbell 31-24 destid rw destination id for srio doorbell, for 16 bit extension 39-32 mask rw programmable srio doorbell mask 47-40 - unused bits 63-48 pointer rw programmable doorbell contents # signal stat description table 94 missing packet programmable flag register
111 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes 9.0 reset and initialization the serb does not require specific power sequencing between any of the core and i/o supplies. figure 11 reset timeline to reset the device, first reset signal has to be de-assert ed (reset low), and it is asserted after 5 ref_clk cycles. 4096 ref_clk cycles later, the device completes the reset process. once completed, access to the serb from any and all interfaces is possible and the serb is fully functional. contro l and data traffic will not be accepted by the serb until this process is fully completed. 9.1 speed select (spd[1:0]) there are 2 port speed select pins. these pins are used to chose the initial speed on srio ports. the selection table is given below: 9.2 srio reset control symbol the srio reset control symbol is defined by the rio spec to perform a master reset on the target device. it is a link level reset and must be received four times to perform the reset. despite it being a control symbol generated at the link level, the use of the reset is generally instructed from higher-level authority than the link. the pps has taken the control symbol and has allowed the user to program the severity of the reset either as a full master reset, or as an srio port reset only. the pps also has the capability of receiving instructions from the dsp to send a control symbol on any one of its ports to reset other attached devices. the serb will not have the capabilities of the pps and will perform only a full master reset whenever the srio reset control symbol has been received four times. the count of four will reset whenever a packet other than an srio reset control symbol is successfully received. the control symbol has no capability to form anything other than a master reset. any other srio resets must be received in the form of type 8 maintenance packets. more details on the control symbol can be found in section 3.4.5.1 of physical layer x1/x4 lp-serial specification. 9.3 jtag reset at power-up, trst must be asserted low to bring the tap controller up in a known, reset state. per ieee 1149.1 specification, the user can alternativel y hold tms pin high while clocking tck five times (minimum) to reset the controller. to deactivate jtag, trst should be tied low so that the tap controller remains in a known state at all times. all of the other jtag input pins are internally biased in such a way that by leaving them unconnected they are automatically disabled. note that jtag inputs are ok to float because t hey have leakers (as required by ieee 1149.1 specification). 9.4 system initialization the serb will automatically configure itself upon power up to the default configuration set by the hard-wired inputs. for the duration of the default configuration, the serb will not acc ept packets on either serial port. once the serb has achieved the default configuration, the ports will become active and ma y accept data. if additional programming is to be completed value on the pins (spd1 spd0) ports rate 00 1.25gbps 01 2.5gbps 10 3.125gbps 11 reserved table 95 port speed selection pin values
112 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes after the default configuration is active, the user should be aw are that data or additional configuration information might be accepted on multiple ports. the user must exercise care to insure that the incoming configuration and data does not inter- fere with the device programming. in many cases, a parti al reset may clear unwanted data, but may cause corruption of active transfers. before operation, the serb must be configured. the steps of configuration are as follows: power on. no power sequencing is required, but all pow er supplies must have achieved the minimum required level before proceeding. master reset may be applied at any time. if reset is performed in association with power on, reset may be applied before, during or after power on, but the reset mu st be held after achieving valid power levels for the designated minimum number of clock cycles (defined in the electrical section). serb will initialize itself according to the hard-wired pins. ? the plls will take time to lock ? the phys will begin to negotiate with neighboring devices, attempting to establish links ? the memory will be allocated, per the default configuration i 2 c may be used for additional programming if required without waiting for pll lock. all of the configuration registers may be programmed through i 2 c. jtag has access to the configuration registers. if jtag is not used for additional programming, the jtag inputs should be disabled. full operation of jtag is described in the jtag section. in the event that the serb needs to be programmed over a serial port, the serial port must have achieved full link up status before programming may commence. if interrupt masks are needed, the masks should be programmed using one of the programming methods. after programming, the serb should be fully functional . it should be noted that the serb may be reconfigured at any time. it should be noted that at any time, the serb may reconfigured through i 2 c or a serial port. 9.5 initialization of rio ports the srio ports shall be initialized before they are operati onal. more needs to be developed on this topic, but as a start, the following references should be made: pps specification an srio port initialization rio physical layer specification section 4.6 rio system bring-up document for explanation and examples of system bring-up hard-wired pin description the initialization of the srio ports may be influenced by the following sources: srio maintenance packets i 2 c programming jtag programming hard-wired inputs
113 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes 10.0 reference clock there are several clocks associated with the serb. all in ternal operational clocks within the serb are generated from the phy reference clock operating at 156.25m hz. the following clocks are used within the serb: 1. phy reference clock. this clock is an input at 156. 25m hz and is used to drive the serial ports and internal functions. when p-port is a qdr memory port, the phy reference clock also drives the memory interface. 2. jtag clock 3. i 2 c clock 10.1 reference clock electrical specifications the reference clock is 156.25 mhz, and is ac-coupled with the following electrical specifications: figure 12 ref_clk representative circuit the reference clock wander should not be more than 100ppm (for 156.25 mhz, this is +/-15.625 khz). this requirement comes from the srio specification that outgoing signals from separate links, which belong to the same port, should not be separated more than 100ppm. note that the series capacitors are descretes that must be pl aced external to the devices?s receivers. all other elements are associated with the input structure internal to the device. v bias is generated internally. name description min nom max units ref_clk ref_clk clock running at 156.25mhz -100 ---- +100 ppm tduty_ref ref_clk duty cycle 40 50 60 % trclk/tfclk input signal rise/fall time (20%-80%) 200 500 650 ps vin_cml differential peak-peak ref_clk input swing 400 ---- 2400 mv rl_clk input termination resistance 40 50 60 ohm li_clk input inductance ----- ----- 4nh ci_clk input capacitance ----- ----- 5pf table 96 input reference clock jitter specifications 5686 drw07 r ef_clk_p r ef_clk_n ref_clk l i ,clk c i ,clk v bias ,clk l i ,clk c i ,clk r l ,clk r l ,clk + -
114 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes 11.0 absolute maximum ratings (1) note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. this is a steady-state dc parameter that applies after the power supply has reached its nominal operating value. power sequencing is not necessary; however, the voltage on any input or i/o pin cannot exceed its corresponding supply voltage during power supply ramp up. 3. ambient temperature under dc bias. no ac conditions. symbol rating commercial & industrial unit v term (v dd 3) v dd 3 terminal voltage with respect to gnd -0.5 to 3.6 v v term (2) (v dd 3-supplied interfaces) input or i/o terminal voltage with respect to gnd -0.3 to v dd 3+0.3 v v term (v dd )v dd terminal voltage with respect to gnd -0.5 to 1.5 v v term (2) (v dd -supplied interfaces) input or i/o terminal voltage with respect to gnd -0.3 to v dd +0.3 v v term (v dds )v dds terminal voltage with respect to gnds -0.5 to 1.5 v v term (2) (v dds -supplied interfaces) input or i/o terminal voltage with respect to gnds -0.3 to v dds +0.3 v v term (v dda )v dda terminal voltage with respect to gnds -0.5 to 1.5 v v term (2) (v dda -supplied interfaces) input or i/o terminal voltage with respect to gnds -0.3 to v dda +0.3 v t bias (3) temperature under bias -55 to +125 c t stg storage temperature -65 to +150 c t jn junction temperature +150 c i out (for v dd 3 = 3.3v) dc output current 30 ma i out (for v dd 3 = 2.5v) dc output current 30 ma table 97 absolute maximum ratings
115 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes 11.1 recommended temperature and operating voltage 1 note: 1. power sequencing is not necessary; however, the vo ltage on any input or i/o pin cannot exceed its corre- sponding supply voltage during power supply ramp up. the dev ice is not sensitive to supply rise and fall times, and thus these are not specified. 2. v dd3 , v dda , and v dds share a common ground (gnds). core supply and ground are v dd and gnd respec- tively. 3. v dd3 may be operated at either 3.3v or 2.5v simply by pr oviding that supply voltage. for those interfaces oper- ating on this supply, this datasheet provides input and output specifications at each of these voltages. 4. v dds & v dda may be tied to a common plane. v dd (core, digital supply) should have its own supply and plane. 11.2 ac test conditions figure 13 ac output test load (jtag) grade ambient temperature max junction temperature (t jn ) ground (2) supply voltage (4) commercial 0 c to 70?c 125 c gnd = 0v gnds = 0v v dd = 1.2 +/- 5% v ddq = 1.5 +/- 5% v dds = 1.2 +/- 5% v dd 3 (3) = 3.3 +/- 5%, or 2.5v +/- 100mv v dda = 1.2 +/- 5% industrial -40 c to 85 c 125?c gnd = 0v gnds = 0v v dd = 1.2 +/- 5% v ddq = 1.5 +/- 5% v dds = 1.2 +/- 5% v dd 3 (3) = 3.3 +/- 5%, or 2.5v +/- 100mv v dda = 1.2 +/- 5% table 98 recommended temperature and operating voltage input pulse levels gnd to 3.0v / gnd to 2.4v input rise / fall times 2ns input timing refer- ence levels 1.5v / 2.5v output reference levels 1.5v / 1.25v output load figure 12 table 99 ac test conditions (v dd3 = 3.3v / 2.5v): jtag, i 2 c, rst
116 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes figure 14 ac output test load (i 2 c) note: 1. the sda and scl pins are open-drain drivers. refer to the philips i 2 c specification [1] for appropriate selec- tion of pull-up resistors for each. figure 15 srio lanes test load note: 1. the characteristic impedance z0 should be designed for 100 ohms. an in line capacitor c1 and c2 at each input of the receiver provides ac-coupling and a dc-b lock. the ist recommended and test value is 100nf for each. thus, ant dc bias differential between the two devic es on the link is negated. the differential input resis- tance is designed to be 100 ohms (per srio specificat ion). thus, r1 and r2 are 50 ohms each. note that v bias is the internal bias voltage of the device?s receiver. 11.3 typical power figures note: 1. values are based on characterization, and are not production tested. typical power draw idd idds idda iddq idd3 4.5w (all supplies) 2.0a 460ma 216ma 465ma 30ma table 100 typical power figures
117 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes 12.0 i 2 c-bus the serb is compliant with the i 2 c specification [1]. this specification provi des all functional detail and electrical speci- fications associated with the i 2 c bus. this includes signaling, addressing, arbi tration, ac timing, dc specifications, and other details. the i 2 c bus is comprised of serial data (sda) and serial clo ck (scl) pins and can be used to attach a cpu for initial- ization and management purposes. a cpu can then access registers and program the device, but it cannot access other devices attached to the srio interfaces through the i 2 c bus. the i 2 c interface supports fast/standard (f/s) mode (400/ 100 khz). the serb does not support cbus or general address calls. 12.1 i 2 c device address relative to i 2 c, the serb is a slave-only receiver and transmitter. the device address for the serb is fully pin-defined by 10 external pins. this provides full flexibility in defin ing the slave address to avoid conflicting with other i 2 c devices on a given bus. the serb may be operated as either a 10-bit addressable device or a 7-bit addressable device based on another external pin address select (ads). if the ads pin is tied to vdd, then the serb operates as a 10-bit addressable device and the device address will be defined as id[9:0]. if the ad s pin is tied to gnd, then the serb operates as a 7-bit addressable device with the device address defined by id[6 :0]. the addressing mode must be established at power-up and remain static throughout operation. dynamic changes will result in undetermined behavior. all of the serb?s registers are addressable through i 2 c. these registers are accessed via 22-bit addresses and 32-bit word boundaries though standard reads and writes. these regi sters may also be accessed through the srio and jtag interfaces. 12.2 signaling the serb is a slave-only receive and transmit devic e. thus, communication with the serb on the i 2 c bus follows these two cases: 1. suppose a master device wants to send information to the serb: ? master device addresses serb (slave) ? master device (master-transmitter), sends data to serb (slave- receiver) ? master device terminates the transfer 2. if a master device wants to receive information from the serb: ? master device addresses serb (slave) ? master device (master-receiver) receives data from serb (slave- transmitter) ? master device terminates the transfer. all signaling is fully compliant with i 2 c. full detail of signaling can be found in the i 2 c specification [1]. pin i 2 c address bit (pin_addr) id0 0 id1 1 id2 2 id3 3 id4 4 id5 5 id6 6 id7 7 (don?t care in 7-bit mode) id8 8 (don?t care in 7-bit mode) id9 9 (don?t care in 7-bit mode) table 101 i 2 c static address selection pin configuration
118 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes 12.2.1 interfacing to standard-, fast-, and hs-mode devices the serb supports fast / standard (f/s) modes of operation. per i 2 c specification, in mixed speed communication the serb supports hs- and fast-mode devices at 400 kbit/s, and st andard-mode devices at 100 kbit/s. please refer to the i 2 c specification for detail on speed negotiation on a mixed speed bus. 12.2.2 serb specific memory access there is a serb-specific i 2 c memory access implementation. this implementation is fully i 2 c compliant. it requires the memory address to be explicitly specified during writes. this provides directed memory accesses through the i 2 c bus. subsequent reads always begin at the address specified during the last write. the write procedure requires the 3-bytes (22-bits) of memory address to be provided following the device address. thus, the following are required: device address ? one or two bytes depending on 10-bit/7-bit addressing, memory address ? 3 bytes yielding 22-bits of memory addre ss, and a 32-bit data payload ? 4 byte words. the read procedure has the memory address section of the transfer removed. thus, to perform a read, the proper access would be to perform a write operation and issue a r epeated start after the acknowledge bit following the third byte of memory address. then, the master would issue a read command selecting the serb through the standard device address procedure with the r/w bit high. note that in 10- bit device address mode (ads=1), only the two msbs need be provided during this read. data from the previously loaded address would immediately follow the device address protocol. it is possible to issue a stop or repeated start anytime duri ng the write data payload procedure, but must be before the final acknowledge (i.e. canceling the write before the actual wr ite operation is completed and performed). also, the master would be allowed to access other devices attached to the i 2 c bus before returning to select the serb for the subsequent read operation from the loaded address. 12.3 figures figure 16 write protocol with 10-bit slave address (ads =1) note: 1. i 2 c writes to memory align on 32-bit word boundaries, thus the 22 address msbs must be provided while the 2 lsbs associated with word and byte pointers are don?t care and are therefore not transmitted. figure 17 read protocol with 10-bit slave address (ads=1) 5686 drw05 device address [9:8] 1110 1 aaaa a data word #1 msb byte data word #1 byte #2 data word #1 byte #3 data word #1 lsb byte r/w bit (r=1, w=0) 817263544 data output is from base mem_addr[21:0] r/w bit (r=1, w=0) 26 17 device address [9:8] a a 8 1110 1 a 35 a 44 data word #1 msb byte a data word #1 byte #2 data word #1 byte #3 data word #1 lsb byte data output is from base mem_addr[21:0]
119 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes figure 18 write protocol with 7-bit slave address (ads=0) note: 1. i 2 c writes to memory align on 32-bit word boundaries, thus the 22 address msbs must be provided while the 2 lsbs associated with word and byte pointers are don?t care and are therefore not transmitted. figure 19 read protocol with 7-bit slave address (ads=0) 12.4 i 2 c dc electrical specifications note that the ads and id pins will all run off the core (1 .2v) power supply, and these pins are required to be fixed during operation. thus, these pins must be st atically tied to the 1.2v supply or gnd. tables 19 and 20 below lists the sda and scl electric al specifications for f/s-mode i 2 c devices: at recommended operating conditions with v dd3 = 3.3v 5% figure 20 i 2 c sda & scl dc electrical specifications 5686 drw06 device address [6:0] 1 aa aa data word #1 msb byte data word #1 byte #2 data word #1 byte #3 data word #1 lsb byte r/w bit (r=1, w=0) 8172635 data output is from base mem_addr[21:0] r/w bit (r=1, w=0) a 26 17 device address [6:0] a a 8 1 a 35 data word #1 msb byte data word #1 byte #2 data word #1 byte #3 data word #1 lsb byte data output is from base mem_addr[21:0]
120 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes at recommended operating conditions with v dd3 = 2.5v 100mv figure 21 i 2 c sda & scl dc electrical specifications 12.5 i 2 c ac electrical specifications figure 22 specifications of the sda and scl bus lines for f/s-mode i 2 c -bus devices note: 1. for more information, see the i2c-bus specification by philips semiconductor [1]. 2. a device must internally provide a hold time of at least 300 ns for the sda signal (referred to the v ihmin of the scl signal) to bridge the undefined region of the falling edge of scl. 3. the maximum t hd ; dat has only to be met if the device does not stretch the low period (t low ) of the scl signal. 4. a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t su ; dat > 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t su ; dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specifi- cation) before the scl line is released.
121 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes 12.6 i 2 c timing waveforms figure 23 i 2 c timing waveforms
122 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes
123 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes 13.0 serial rapidio tm ac specifications 13.1 overview the serb?s serdes are in full compliance to the rapidio tm ac specifications for the lp-serial physical layer [5]. this section provides those specifications fo r reference. the electrical specificati ons cover both single and multiple-lane links. two transmitters (short run and long run) and a single receiver are specified for each of three baud rates, 1.25, 2.50, and 3.125 gbaud. two transmitter specifications allow for solutions ranging from chip-to-chip interconnect to driving two connectors across a backplane. a single receiver specification is given that will accept signals from both the short run and long run transmitter specifications. the short run transmitter should be used mainly for chip-to- chip connections on either the same printed circuit board or across a single connector. this covers the case wher e connections are made to a mezzanine (daughter) card. the minimum swings of the short run specification reduce the overall power used by the transceivers. the long run transmitter specifications use larger voltage sw ings that are capable of dr iving signals across backplanes. this allows a user to drive signals across two connectors and a backplane. the serb can drive beyond the specification distance of at least 50 cm at all baud rates. please use idt?s simulation kit io models to determine reach and signal quality for a given pcb design. all unit intervals are specified with a tolerance of +/- 100 ppm. the worst case frequency difference between any transmit and receive clock will be 200 ppm. to ensure inter-operability between drivers and receivers of different vendors and technologies, ac coupling at the receiver input must be used. 13.2 signal definitions lp-serial links uses differential signaling. this section defi nes terms used in the description and specification of differ- ential signals. differential peak-peak voltage of transmitter or receiver shows how the signals are defined. the figure below shows waveforms for either a transmitter output (td and td ) or a receiver input (rd and rd ). each signal swings between a volts and b volts where a > b. using these waveforms, the definitions are as follows: 1. the transmitter output signals and the receiver input signals td, td , rd and rd each have a peak-to-peak swing of a - b volts 2. the differential output signal of the transmitter, v od , is defined as v td -v td . 3. the differential input signal of the receiver, v id , is defined as v rd -v rd . 4. the differential output signal of the transmitter and the differential input signal of the receiver each range from a - b to -(a - b) volts. 5. the peak value of the differential transmitter output signal and the differential receiver input signal is a - b volts 6. the peak-to-peak value of the differential transmitter output signal and the 7. differential receiver input signal is 2 * (a - b) volts figure 24 differential peak-peak voltage of transmitter or receiver
124 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes to illustrate these definitions using real values, consider the case of a cml (current mode logic) transmitter that has a common mode voltage of 2.25 v and each of its outputs, td and td , has a swing that goes between 2.5v and 2.0v. using these values, the peak-to-peak voltage swing of the signals td and td is 500 mv p-p. the differential output signal ranges between 500 mv and -500 mv. the peak differential voltage is 500 mv. the peak-to-peak differential voltage is 1000 mv p- p. 13.3 equalization with the use of high speed serial links, the interconnect m edia will cause degradation of the signal at the receiver. effects such as inter-symbol interference (isi) or data dependent jitter are produced. this loss can be large enough to degrade the eye opening at the receiver beyond what is allowed in the specification. to negate a portion of these effects, equalization can be used. the equalization technique implement ed in the serb is pre-emphasis on the transmitter (under register control) 13.4 explanatory note on transmitter and receiver specifications ac electrical specifications are giv en for transmitter and receiver. long run and short run interfaces at three baud rates (a total of six cases) are described. the parameters for the ac electrical specifications are guided by the xaui electrical interface specified in clause 47 of ieee 802.3ae-2002. xaui has similar application goals to serial rapidio tm . the goal of this standard is that electrical designs for serial rapidio tm can reuse electrical designs for xaui, suitably m odified for applications at the baud intervals and reaches described herein. 13.5 transmitter specifications lp-serial transmitter electrical and ti ming specifications are stated in the text and tables of this section. the differential return loss, s11, of the transmitter in each case shall be better than -10 db for (baud frequency)/10 < freq(f) < 625 mhz, and -10 db + 10log(f/625 mhz) db for 625 mhz <= freq(f) <= baud frequency the reference impedance for the differential return loss m easurements is 100 ohm resistive. differential return loss includes contributions from on-chip circuitry, chip packagi ng and any off-chip components related to the driver. the output impedance requirement applies to all valid output levels. the 80KSBR200 satisfies the specification requirement that t he 20%-80% rise/fall time of the transmitter, as measured at the transmitter output, in each case have a minimum value 60 ps. similarly the timing skew at the output of an lp-serial trans mitter between the two signals that comprise a differential pair not exceed 25 ps at 1.25 gb, 20 ps at 2.50 gb and 15 ps at 3.125 gb. figure 25 short run transmitter ac timing specifications - 1.25 gbaud
125 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes figure 26 short run transmitter ac timing specifications - 2.5 gbaud figure 27 short run transmitter ac timing specifications - 3.125 gbaud figure 28 long run transmitter ac timing specifications - 1.25 gbaud
126 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes figure 29 long run transmitter ac timing specifications - 2.5 gbaud figure 30 long run transmitter ac timing specifications - 3.125 gbaud for each baud rate at which an lp-serial transmitter is specif ied to operate, the output eye pattern of the transmitter shall fall entirely within the un-shaded portion of the transmitter output compliance mask shown in figure 30 with the parameters specified in figure 31 . the eye pattern is measured at the output pi ns of the device and the device is driving a 100 ohm +/- 5% differential resistive load. the output eye patte rn of a lp-serial transmitter that implements pre-emphasis (to equalize the link and reduce inter-symbol interference) need only comply with the transmitter output compliance mask when pre-emphasis is disabled or minimized.
127 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes figure 31 transmitter output compliance mask figure 32 transmitter differential output eye diagram parameters 13.6 receiver specifications lp-serial receiver electrical and timing specifications are stated in the text and tables of this section. receiver input impedance shall result in a differential return loss better that 10 db and a common mode return loss better than 6 db from 100 mhz to (0.8)*(baud frequency). this includes contributions from on-chip circuitry, the chip package and any off-chip components related to the receiver . ac coupling components are included in this requirement. the reference impedance for return loss measurements is 100 ohm resistive for differential return loss and 25 ohm resis- tive for common mode.
128 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes figure 33 receiver ac timing specifications - 1.25 gbaud note: 1. total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. the sinusoidal jitter may have any amplitude and frequency in the un-shaded region of figure 35 . the sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects figure 34 receiver ac timing specifications - 2.5 gbaud note: 1. total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. the sinusoidal jitter may have any amplitude and frequency in the un-shaded region of figure 35 . the sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.
129 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes figure 35 receiver ac timing specifications - 3.125 gbaud note: 1. total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. the sinusoidal jitter may have any amplitude and frequency in the un-shaded region of figure 35 . the sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects. figure 36 single frequency sinusoidal jitter limits
130 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes 13.6.1 receiver eye diagrams for each baud rate at which an lp-serial receiver is specified to operate, the receiver meets the corresponding bit error rate specification (receiver ac timing specificati on - 1.25 gbaud, receiver ac timing specification - 2.5 gbaud, and receiver ac timing specification - 3.125 gbaud) when the eye pattern of the receiver test signal (exclusive of sinuso- idal jitter) falls entirely within the un-shaded portion of the receiver input compliance mask shown in figure 36 with the parameters specified in figure 37 . the eye pattern of the receiver test signal is measured at the input pins of the receiving device with the device replaced with a 100 ohm +/- 5% differential resistive load. figure 37 receiver input compliance mask figure 38 receiver input compliance mask parameters exclusive of sinusoidal jitter
131 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes 14.0 parallel port electrical characteristics the parallel port on the serb can connect to a qdrii-b4 x 36 sram. the serb acts as a memory controller and drives the external sram. the p-port may also be disabled. the electrical requirements of the p-port are simply must be qdrii compatible. as a fifo controller, the serb must be burst 4 compatible. included in the parallel port requirements is the need for programmable output impedance as is used in the qdrii sram. this includes the attachment of an external resistor to set the impedance. the serial interface operate at 3.125g bps with 8b/10b encoding on each lane. after decoding and alignment of the four lanes, the maximum data rate is 10g bps across the interfac e in each direction. the external memories are all burst of four. the clock rate on the bus is specified at 156.25 mhz. the 156.25 mhz is sufficient to support the 10g bps total band- width in each direction necessary on the p-port. please refer to figure below for serb to external qdrii sram interface connections. figure 39 p-port signals connected to a qdrii sram 14.1 ac electrical characteristics in this mode, the p-port electrical characteristics and in terface shall be fully compliant with designated qdrii sram devices at hstl levels. while qdrii has the ability to operate at 1.8v and other voltages in between 1.8v and hstl, there is no requirement for the serb to operate beyond hstl. there will be a direct connection from the p-port to the memory. the drive requirements of the interface will be hstl cl ass 1 or less. there is a zq pin for setting interface imped- ance. when connected to a qdr memory, the specific needs of the qdrii device must be met. the p-port to qdr sram clocking include the following: the p-port output clock / qdr input clock shall be center aligned and designed to clock the qdrii sram k/ k# input clock. the p-port input clock shall be edge aligned and designed to connect to the cq/cq# output of the qdrii sram. it is strongly suggested that the c/c# clocks not be returned to the serb p-port. the serbs phy clock is used internally to generate the p-port output clock please refer to table below for specific ac electrical characteristics requirements. serial buffer p-port address(23) k, k# (center) rd# wr# q(36) d(36) cq, cq# (edge) qdr2 sram k, k# c/ c# bw(4) wr# rd# d(36) q(36) cq, cq# sa
132 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes note: 1. clock phase jitter is the variance from clo ck rising edge to the next expected clock rising edge. 2. vdd slew rate must be less than 0.1v dc per 50ns for dll lock retention. dll lock time begins once vdd and input clock are stable. 3. if c, c are tied high, k, k become the references for c, c timing parameters. 4. all address inputs must meet the specified setup and hold times for all latching clock edges. 5. clock high time (tkhkl) and clock low time (tklkh) should be within 40% to 60% of the duty cycle time (tkhkh). 6. clock to clock time (tkhk h) and clock to clock time (tk hkh) should be within 45% to 55% of the duty cycle time (tkhkh). 156.25mhz symbol parameter min. max. unit notes clock parameters tkhkh clock cycle time (k,k ,c,c ) 6.00 8.40 ns tkc var clock phase jitter (k,k ,c,c ) - 0.20 ns 1 tkhkl clock high time (k,k ,c,c )2.40-ns5 tklkh clock low time (k,k ,c,c )2.40-ns5 tkhk h clock to clock (k k ,c c )2.70-ns6 tk hkh clock to clock (k k,c c) 2.70 - ns 6 tkhch clock to data clock (k c,k c ) 0.00 2.80 ns tck lock dll lock tim (k, c) 1024 - cycles 2 tkc reset k static to dll reset 30 - ns output parameters tchqv c, c high to output valid - 0.50 ns 3 tchqx c, c high to output hold -0.50 - ns 3 tchcqv c, c high to echo clock valid - 0.50 ns 3 tchcqx c, c high to echo clock hold -0.50 - ns 3 tcqhqv cq, cq high to output valid - 0.40 ns tcqhqx cq, cq high to output hold -0.40 - ns tchqz c high to output high-z - 0.50 ns 3 tchqx1 c high to output low-z -0.50 - ns 3 set-up times tavkh address valid to k, k rising edge 0.50 - ns 4 tivkh r , w inputs valid to k, k rising edge 0.50 - ns tdvkh data-in valid to k, k rising edge 0.50 - ns hold times tkhax k, k rising edge to address hold 0.50 - ns 6 tkhix k, k rising edge to r , w inputs hold 0.50 - ns tkhdx k, k rising edge to data-in hold 0.50 - ns table 102 ac electrical characteristics
133 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes figure 40 timing waveform of combined read and write cycles 6 1 0 9 d r w 0 9 a k k 1 2 3 r sa q tkhch tkhkl tkhix tivkh tkhax tavkh c c cq c q tchqx tchqx1 tklkh tc hcqv tch cq x w d tkhdx tdvk h 4 5 67 8 9 10 tklkh tkhkh tkh k h a0 a3 a2 a1 a4 a5 a6 tkhax tavkh d10 d11 d30 d31 d50 d51 d60 d61 tkhdx tdvkh q00 q01 q20 q21 q40 q41 tchqz tc hqv tchqv tc hq x tcqhqv tkhch tkhkl tkh k h tkhkh tchcqx tchcqv r e a d a 0 w r i t e a 1 r e a d a 2 r e a d a 4 nop n o p n o p w r i t e a 3 w r i t e a 5 w r i t e a 6 tc q h q x
134 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes
135 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes 15.0 jtag interface the 80KSBR200 offers full jtag (boundary scan) support for both its slow speed and high speed pins. this allows ?pins-down? testing of newly manufactured printed circuit boards as well as troubleshooting of field returns. the jtag tap interface also offers an alternative method for configur ation register access (cra) (along with the srio and i 2 c ports). thus this port may be used for programming the serb?s many registers. boundary scan testing of the ac-coupled ios is performed in accordance with ieee 1149.6 (ac extest). 15.1 ieee 1149.1 (jtag) & ieee 1149.6 (ac extest) compliance all dc pins are in full compliance with ieee 1149.1 [10]. all ac-coupled pins fully comply with ieee 1149.6 [11]. all 1149.1 and 1149.6 boundary scan cells are on the same chain. no additional control cells are provided for independent selection of negative and/or positive terminals of the tx- or rx-pairs. 15.2 system logic tap controller overview the system logic utilizes a 16-state, six-bit tap controller, a four-bit instruction register, and five dedicated pins to perform a variety of functions. the primary use of the jtag ta p controller state machine is to allow the five external jtag control pins to control and access the serb's many external signal pins. the jtag tap controller can also be used for identifying the device part number. the jtag logic of the 80KSBR200 is depicted in the figure below. figure 41 diagram of the jtag logic 15.3 signal definitions jtag operations such as reset, state-transition control and clock sampling are handled through the signals listed in the table below. a functional overview of the tap controller and boundary scan registers is provided in the sections following the table. pin name type description trst input jtag reset asynchronous reset for jtag tap controller (internal pull-up) tck input jtag clock test logic clock. jtag_tms and jtag_tdi are sampled on the rising edge. jtag_tdo is output on the falling edge. tms input jtag mode select. requires an external pull-up. controls the state transitions for the tap controller state machine (internal pull-up) table 103 jtag pin descr iptions (part 1 of 2) bypass register instruction register decoder 4-bit instruction register tap controller m u x m u x device id register boundary scan register tdi tms tck trst tdo
136 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes the system logic tap controller transitions from state to st ate, according to the value present on jtms, as sampled on the rising edge of tck. the test-logic reset state can be reached either by asserting trst or by applying a 1 to tms for five consecutive cycles of tck. a state diagram for the tap controller appears in figure 41 . the value next to state repre- sent the value that must be applied to tms on the next rising edge of tck, to transition in the direction of the associated arrow. figure 42 state diagram of the 80KSBR200?s tap controller 15.4 test data register (dr) the test data register contains the following: the bypass register the boundary scan registers the device id register these registers are connected in parallel between a comm on serial input and a common serial data output, and are described in the following sections. for more detailed descriptions, refer to ieee standard test access port (ieee std. 1149.1-1990). tdi input jtag input serial data input for bsc chain, instruction register, idcode register, and bypass register (internal pull-up) tdo output jtag output serial data out. tri-stated except when shifting while in shift-dr and shift-ir tap controller states. pin name type description table 103 jtag pin descr iptions (part 2 of 2) test- logic reset run-test/ idle select- dr-scan capture-dr shift-dr exit1 -dr pause-dr exit2-dr select- ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-dr update-ir 11 0 0 0 1 1 0 0 1 1 0 1 0 1 0 0 1 1 1 0 0 11 0 1 0 1 1 0 00 0
137 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes 15.4.1 boundary scan registers the 80KSBR200 boundary scan chain is 140 bits long. the five jtag pins do not have scan elements associated with them. full boundary scan details can be found in the associated bsdl file which may be found on our web site (www.idt.com). the boundary scan chain is connected bet ween tdi and tdo when the extest or sample/preload instructions are selected. once extest is selected and the tap controller passes through the update-ir state, what- ever value that is currently held in the boundary scan register?s output latches is immediately transferred to the corre- sponding outputs or output enables. therefore, the sample/preload instruction must first be used to load suitable values into the boundary scan cells, so that inappropriate values are not driven out onto the system pins. all of the boundary scan cells feature a negative edge latch, which guarantees that clock skew cannot cause incorrect data to be latched into a cell. the input cells are sample- only cells. the simplified logic configurati on is shown in the figure below. figure 43 diagram of observe-only input cell the simplified logic configuration of the output cells is shown in the figure below. figure 44 diagram of output cell input pin shift_dr from previous cell clock_dr dq to next cell to core logic mux data from core data from previous cell shift_dr to next cell to output pad clock_dr update_dr mux d q dq extest mux
138 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes the output enable cells are also output cells. the simplified logic appears in the figure below. figure 45 diagram of output enable cell the bidirectional cells are composed of only two boundar y scan cells. they contain one output enable cell and one capture cell, which contains only one register. the input to this single register is selected via a mux that is selected by the output enable cell when extest is disabled. when the output enable cell is driving a high out to the pad (which enables the pad for output) and extest is disabled, the capture cell will be configured to capture output data from the core to the pad. however, in the case where the output enable cell is low (signifying a tri-state condition at the pad) or extest is enabled, the capture cell will capture input data from the pad to the core. the configuration is shown graphically in the figure below. figure 46 diagram of bidirectional cell dq d q from core data from previous cell extest to output enable clock_dr shift_dr update_dr output enable to next cell mux mux from previous cell output enable cell output enable from core extest output from core input to core capture cell to next cell i/o pin mux
139 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes 15.5 instruction register (ir) the instruction register allows an instruction to be shifted serially into the serb at the rising edge of tck. the instruc- tion is then used to select the test to be performed or the test register to be accessed, or both. the instruction shifted into the register is latched at the completion of the shifting pr ocess, when the tap controller is at the update-ir state. the instruction register contains four shift-register-based cells that can hold in struction data. this register is decoded to perform the following functions: to select test data registers that may operate while the instruction is current. the other test data registers should not interfere with chip operation and selected data registers. to define the serial test data register path used to shift data between tdi and tdo during data register scanning. the instruction register is comprised of 4 bits to decode instructions, as shown in the table below. 15.5.1 extest the external test (extest) instruction is used to control the boundary scan register, once it has been initialized using the sample/preload instruction. using extest, the user can then sample inputs from or load values onto the external pins of the 80KSBR200. once this instruction is selected, the user then uses the shift-dr tap controller state to shift values into the boundary scan chain. when the tap controller passes through the update-dr state, these values will be latched onto the output pins or into the output enables. instruction definition opcode [3:0] extest mandatory instruction allowing the testing of board level interconnections. data is typi- cally loaded onto the latched parallel outputs of the boundary scan shift register using the sample/preload instruction prior to use of the extest instruction. extest will then hold these values on the outputs while being executed. also see the clamp instruction for similar capability. 0000 sample/ preload mandatory instruction that allows data values to be loaded onto the latched parallel out- put of the boundary-scan shift register prior to selection of the other boundary-scan test instruction. the sample instruction allows a snapshot of data flowing from the system pins to the on-chip logic or vice versa. 0001 idcode provided to select device identification to read out manufacturer?s identity, part, and version number. 0010 highz tri-states all output and bidirectional boundary scan cells. 0011 clamp provides jtag user the option to bypass the part?s jtag controller while keeping the part outputs controlled similar to extest. 0100 extest_pulse ac extest instruction implemented in accordance with the requirements of the ieee std. 1149.6 specification. 0101 extest_train ac extest instruction implemented in accordance with the requirements of the ieee std. 1149.6 specification. 0110 reserved behaviorally equivalent to the bypass instruction as per the ieee std. 1149.1 specifi- cation. however, the user is advised to use the explicit bypass instruction. 0111 ? 1001 configura- tion register access (cra) serb-specific opcode to allow reading and writing of the configuration registers. reads and writes must be 32-bits. see further detail below. 1010 private for internal use only. do not use. 1011 ? 1100 shift fuse status to shift the internal fuse status out to tdo pin. 1101 private for internal use only. do not use. 1110 bypass the bypass instruction is used to truncate the boundary scan register as a single bit in length. 1111 table 104 instructions supported by 80KSBR200?s jtag boundary scan
140 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes 15.5.2 sample/preload the sample/preload instruction has a dual use. the primary use of this instruction is for pre-loading the boundary scan register prior to enabling the extest instruction. failure to preload will result in unknown random data being driven onto the output pins when extest is selected. the secondary function of sample/preload is for sampling the system state at a particular moment. using the sample function, the user can halt the device at a certain state and shift out the status of all of the pins and output enables at that time. 15.5.3 bypass the bypass instruction is used to truncate the boundary scan r egister to a single bit in length. during system level use of the jtag, the boundary scan chains of all the devices on the board are connected in series. in order to facilitate rapid testing of a given device, all other devices are put into by pass mode. therefore, instead of having to shift 140 times to get a value through the 80KSBR200, the user only needs to shift one time to get the value from tdi to tdo. when the tap controller passes through the capture-dr state, the value in the bypass register is updated to be 0. if the device being used does not have an idcode register, then the bypass instruction will automatically be selected into the instruction register whenever the tap controller is re set. therefore, the first value that will be shifted out of a device without an idcode register is always 0. devices such as the 80KSBR200 that include an idcode register will automatically load the idcode instruction when the tap controller is reset, and they will shift out an initial value of 1. this is done to allow the user to easily distinguish betw een devices having idcode registers and those that do not. 15.5.4 clamp this instruction, listed as optional in the ieee 1149.1 jt ag specifications, allows the boundary scan chain outputs to be clamped to fixed values. when the clamp instruction is issued, the scan chain will bypass the 80KSBR200 and pass through to devices further down the scan chain. 15.5.5 idcode the idcode instruction is automatically loaded when the tap cont roller state machine is reset either by the use of the trst signal or by the application of a ?1? on tms for five or mo re cycles of tck as per the ieee std 1149.1 specification. the least significant bit of this value must always be 1. therefore, if a device has a idcode register, it will shift out a 1 o n the first shift if it is brought directly to the shift-dr tap controller state after the tap controller is reset. the board- le vel tester can then examine this bit and determine if the device contai ns a device_id register (the first bit is a 1), or if the device only contains a bypass register (the first bit is 0). however, even if the device contains an idcode register, it must also contain a bypass register. the only difference is that the bypass register will not be the default register selected during the tap controller reset. when the idcode instruction is active and the tap controller is in the shift-dr state, the thirty-two bit value that will be shifted out of the device-id register is 0x004f0037 . bit(s) mnemonic description r/w reset 0 reserved reserved 0x1 r 1 11:1 manuf_id manufacturer identity (11 bits) idt 0x33 r0x033 27:12 part_number part number (16 bits) this field identifies the part number of the processor derivative. for the 80KSBR200 this value is: 0x04f0 rimpl. dep. 31:28 version version (4 bits) this field identifies the version number of the processor derivative. for the 80KSBR200, this value is 0x0 rimpl. dep. table 105 system controller device identification register
141 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes 15.5.6 extest pulse this ieee 1149.6 instruction applies only to the ac-coupled pins. all dc pins will perform as if the ieee std 1149.1 extest instruction is operating whenever the extest_pulse instruction is effective. the extest_pulse instruction enables edge-detecting behav ior on signal paths containing ac pins, where test receivers reconstruct the original waveform created by a driver even when signals decay due to ac-coupling. as the operation name suggests, enabling extest_pulse c auses a pulse to be issued which can be detected even on ac-coupled receivers. refer to the ieee std 1149.6 for full details. below is a short synopsis. if enabled, the output signal is forced to the value in its asso ciated boundary-scan register data cell for its driver (true and inverted values for a differential pair) at the falling edg e of tck in the update-ir and update-dr tap controller states. the output subsequently transitions to the opposite of t hat state (an inverted state) on the first falling edge of tck that occurs after entering the run-test/idle tap controller st ate. it then transitions back again to the original state (a non- inverted state) on the first falling edge of tck afte r leaving the run-test/idle tap controller state. 15.5.7 extest train this ieee 1149.6 instruction applies only to the ac-coupled pins. all dc pins will perform as if the ieee std 1149.1 extest instruction is operating whenever the extest_pulse instruction is effective. the extest_train instruction enables edge-detecting behav ior on signal paths containing ac pins, where test receivers reconstruct the original waveform created by a driver even when signals decay due to ac-coupling. as the operation name suggests, enabling extest_train caus es a pulse train to be issued which can be detected even on ac-coupled receivers. once in an enabled state, the trai n will be sent continuously in response to the tck clock. no other signaling is required to generate the pulse train while in this state. refer to the ieee std 1149.6 for full details. below is a short synopsis. first, the output signal is forced to the state matching the value (a non-inverted state) in its associated boundary-scan register data cell for its driver (true and inverted values for a differential pair), at the falling edge of tck in update-ir. then the output signal transitions to the opposite state (an inverted state) on the first falling edge of tck that occurs after entering the run-test/idle tap controller state. while remaining in this state, the output signal will continue to invert on every falling edge of tck, thereby generating a pulse train. 15.5.8 reserved reserved instructions implement various test modes used in the device manufacturing process. the user should not enable these instructions. 15.5.9 private private instructions implement various test modes used in the device manufacturing process. the user should not enable these instructions. 15.6 usage considerations as previously stated, there are internal pull-ups on trst , tms, and tdi. however, tck also needs to be driven to a known value. it is best to either drive a zero on the tck pin when it is not being used or to use an external pull-down resistor. in order to guarantee that the jtag does not interfere with normal system operation, the tap controller should be forced into the test-logic-reset controller state by continuously holding trst low and/or tms high when the chip is in normal operation. if jtag will not be used, externally pull-down trst low to disable it. version part number manuf id lsb 0000 0000|0100|1111|0000 0000|0011|011 1 figure 106 system controller device id instruction format
142 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes 15.7 jtag configuration register access as previously mentioned, the jtag port may be used to read and write to the 80KSBR200?s configuration registers. the same jtag instruction (4b1010) is used for both writes and reads. table 107 data stream for jtag configuration register access mode 15.7.1 writes during configuration register access a write is performed by shifting the cra opcode into the inst ruction register (ir), then shifting in first a read / write select bit, then both the 22-bit target address and 32-bit data into the data register (dr). when bit 0 of the data stream is 0, data shifted in after the address will be written to the addr ess specified in jtag_config_addr. the tdo pin will transmit al l 0s. see the figure below for the associated timing diagram. figure 47 implementation of write during configuration register access 15.7.2 reads during configuration register access reads are much like writes except that target data is not provided. when bit 0 of the data stream is 1, data shifted out will be read from the address specified in jtag_config_addr. tdi will not be used after the address is shifted in. as a func- tion of read latency in the architecture, the first 16 bits wi ll be 0?s and must be ignored. the following bits will contain th e actual register bits. bits field name size description 0 jtag_config_wr_n 1 1 ? read configuration register 0 ? write configuration register [22:1] jtag_config_addr 22 starting address of the memory mapped configuration register. 22 address bits map to a unique double-word aligned on a 32-bit bound- ary. this provides accessibility to and is consistent with the srio memory mapping. [54:23] jtag_config_data 32 reads: data shifted out (one 32-bit word per read) is read from the configuration register at address jtag_config_addr. writes: data shifted in (one 32-bit word per write) is written to the con- figuration register at address jtag_config_addr.
143 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes figure 48 implementation of read during configuration register access 15.8 jtag dc electrical specifications at recommended operating conditions with v dd3 = 3.3v 5% figure 49 jtag dc electrical specifications (v dd3 = 3.3v 5%) at recommended operating conditions with v dd3 = 2.5v 100mv figure 50 jtag dc electrial specifications (v dd3 = 2.5v 100mv )
144 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. notes 15.9 jtag ac electrical specifications figure 51 jtag ac electrical specifications note: 1. guaranteed by design. 2. 30pf loading on external output signals. 3. refer to ac electrical test conditions stated earlier in this document. 4. jtag operations occur at one speed (10mhz). the base device may run at any speed specified in this datasheet. 15.10 jtag timing specification figure 52 jtag timing specifications note: 1. device inputs = all device inputs except tdi, tms, and trst. 2. device outputs = all device outputs except tdo. 80KSBR200 symbol parameter min. max. units t jcyc jtag clock input period 100 ____ ns t jch jtag clock high 40 ____ ns t jcl jtag clock low 40 ____ ns t jr jtag clock rise time ____ 3 (1) ns t jf jtag clock fall time ____ 3 (1) ns t jrst jtag reset 50 ____ ns t jrsr jtag reset recovery 50 ____ ns t jcd jtag data output ____ 25 ns t jdc jtag data output hold 0 ____ ns t js jtag setup 15 ____ ns t jh jtag hold 15 ____ ns 5686 tbl 0 2 range unit notes symbol parameter min. max. v o output voltage -0.40 2.30 volts voltage relative to common of either signal comprising a differential pair v diff pp differential output voltage 800 1600 mv p-p j d deterministic jitter ____ 0.17 ui p-p j t total jitter ____ 0.35 ui p-p s mo multiple output skew ____ 1000 ps skew at the transmitter output between lanes of a multilane link ui unit interval 320 320 ps +/- 100 ppm 5686 tbl 08
145 of 172 march 19, 2007 ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. idt 80KSBR200 advanced datasheet* 16.0 pinout & pin listing 16 .1 pinout figure 53 80KSBR200 pinout
146 of 172 march 19, 2007 ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. idt 80KSBR200 advanced datasheet* 16.2 pin listing table 108 pin listing (alphabetical) pin number pin name function supply / interface pin function description v17 a0 qdr addr 0 (vddq, gnd) / cmos output when operating as a fifo controller, the a output is the address for the external memory and should be connected directly to the sa lines on the qdrii b4 sram. ab19 a1 qdr addr 1 (vddq, gnd) / cmos output when operating as a fifo controller, the a output is the address for the external memory and should be connected directly to the sa lines on the qdrii b4 sram. w17 a2 qdr addr 2 (vddq, gnd) / cmos output when operating as a fifo controller, the a output is the address for the external memory and should be connected directly to the sa lines on the qdrii b4 sram. ab20 a3 qdr addr 3 (vddq, gnd) / cmos output when operating as a fifo controller, the a output is the address for the external memory and should be connected directly to the sa lines on the qdrii b4 sram. aa18 a4 qdr addr 4 (vddq, gnd) / cmos output when operating as a fifo controller, the a output is the address for the external memory and should be connected directly to the sa lines on the qdrii b4 sram. aa20 a5 qdr addr 5 (vddq, gnd) / cmos output when operating as a fifo controller, the a output is the address for the external memory and should be connected directly to the sa lines on the qdrii b4 sram. y18 a6 qdr addr 6 (vddq, gnd) / cmos output when operating as a fifo controller, the a output is the address for the external memory and should be connected directly to the sa lines on the qdrii b4 sram. aa21 a7 qdr addr 7 (vddq, gnd) / cmos output when operating as a fifo controller, the a output is the address for the external memory and should be connected directly to the sa lines on the qdrii b4 sram. w18 a8 qdr addr 8 (vddq, gnd) / cmos output when operating as a fifo controller, the a output is the address for the external memory and should be connected directly to the sa lines on the qdrii b4 sram. y20 a9 qdr addr 9 (vddq, gnd) / cmos output when operating as a fifo controller, the a output is the address for the external memory and should be connected directly to the sa lines on the qdrii b4 sram. w19 a10 qdr addr 10 (vddq, gnd) / cmos output when operating as a fifo controller, the a output is the address for the external memory and should be connected directly to the sa lines on the qdrii b4 sram. y21 a11 qdr addr 11 (vddq, gnd) / cmos output when operating as a fifo controller, the a output is the address for the external memory and should be connected directly to the sa lines on the qdrii b4 sram. v19 a12 qdr addr 12 (vddq, gnd) / cmos output when operating as a fifo controller, the a output is the address for the external memory and should be connected directly to the sa lines on the qdrii b4 sram. aa22 a13 qdr addr 13 (vddq, gnd) / cmos output when operating as a fifo controller, the a output is the address for the external memory and should be connected directly to the sa lines on the qdrii b4 sram.
147 of 172 march 19, 2007 ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. idt 80KSBR200 advanced datasheet* aa19 a14 qdr addr 14 (vddq, gnd) / cmos output when operating as a fifo controller, the a output is the address for the external memory and should be connected directly to the sa lines on the qdrii b4 sram. y22 a15 qdr addr 15 (vddq, gnd) / cmos output when operating as a fifo controller, the a output is the address for the external memory and should be connected directly to the sa lines on the qdrii b4 sram. v21 a16 qdr addr 16 (vddq, gnd) / cmos output when operating as a fifo controller, the a output is the address for the external memory and should be connected directly to the sa lines on the qdrii b4 sram. w22 a17 qdr addr 17 (vddq, gnd) / cmos output when operating as a fifo controller, the a output is the address for the external memory and should be connected directly to the sa lines on the qdrii b4 sram. v18 a18 qdr addr 18 (vddq, gnd) / cmos output when operating as a fifo controller, the a output is the address for the external memory and should be connected directly to the sa lines on the qdrii b4 sram. v22 a19 qdr addr 19 (vddq, gnd) / cmos output when operating as a fifo controller, the a output is the address for the external memory and should be connected directly to the sa lines on the qdrii b4 sram. u18 a20 qdr addr 20 (vddq, gnd) / cmos output when operating as a fifo controller, the a output is the address for the external memory and should be connected directly to the sa lines on the qdrii b4 sram. c6 ads i 2 c (vdd, gnd) / cmos input i 2 c address width select. set ads = gnd for 7-bit serb slave address. ads = vdd for 10-bit. note: supply / levels requirements are unque from the other i 2 c pins. u3 auxcki aux clocki auxiliary clocks provided to bypass cdr block for dc-type test- ing of serdes rx inputs. v3 auxckq aux clockq auxiliary clocks provided to bypass cdr block for dc-type test- ing of serdes rx inputs. e21 cki p-port clock (vdd, gnd) / cmos input clock input for the p-port. these inputs should be connected to the cq/ncq outputs of the qdr sram when operating as a fifo controller. e22 cki_n p-port clock (vdd, gnd) / cmos input clock input for the p-port. these inputs should be connected to the cq/ncq outputs of the qdr sram when operating as a fifo controller. h18 cko echo clock (vdd, gnd) / cmos output clock output that is closely aligned with parallel port data output (q), address (a), queue empty (e), and queue full (f). when operating as a fifo controller, outputs read (nrd), and write (nwr) are also aligned. the alignment is selectable as either cen- ter aligned or edge aligned in the configuration register. when ppm is low, this output should be connected to the k and nk inputs of the qdr sram. g18 cko_n echo clock (vdd, gnd) / cmos output clock output that is closely aligned with parallel port data output (q), address (a), queue empty (e), and queue full (f). when operating as a fifo controller, outputs read (nrd), and write (nwr) are also aligned. the alignment is selectable as either cen- ter aligned or edge aligned in the configuration register. when ppm is low, this output should be connected to the k and nk inputs of the qdr sram.
148 of 172 march 19, 2007 ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. idt 80KSBR200 advanced datasheet* c13 d0 qdr sram data in 0 (vddq, gnd) / cmos input the qdr input data bus 0 a16 d1 qdr sram data in 1 (vddq, gnd) / cmos input the qdr input data bus 1 d14 d2 qdr sram data in 2 (vddq, gnd) / cmos input the qdr input data bus 2 f20 d3 qdr sram data in 3 (vddq, gnd) / cmos input the qdr input data bus 3 b16 d4 qdr sram data in 4 (vddq, gnd) / cmos input the qdr input data bus 4 c14 d5 qdr sram data in 5 (vddq, gnd) / cmos input the qdr input data bus 5 d22 d6 qdr sram data in 6 (vddq, gnd) / cmos input the qdr input data bus 6 a17 d7 qdr sram data in 7 (vddq, gnd) / cmos input the qdr input data bus 7 b14 d8 qdr sram data in 8 (vddq, gnd) / cmos input the qdr input data bus 8 d21 d9 qdr sram data in 9 (vddq, gnd) / cmos input the qdr input data bus 9 e15 d10 qdr sram data in 10 (vddq, gnd) / cmos input the qdr input data bus 10 b22 d11 qdr sram data in 11 (vddq, gnd) / cmos input the qdr input data bus 11 b17 d12 qdr sram data in 12 (vddq, gnd) / cmos input the qdr input data bus 12 d15 d13 qdr sram data in 13 (vddq, gnd) / cmos input the qdr input data bus 13 c21 d14 qdr sram data in 14 (vddq, gnd) / cmos input the qdr input data bus 14 a18 d15 qdr sram data in 15 (vddq, gnd) / cmos input the qdr input data bus 15 c15 d16 qdr sram data in 16 (vddq, gnd) / cmos input the qdr input data bus 16 e19 d17 qdr sram data in 17 (vddq, gnd) / cmos input the qdr input data bus 17 c17 d18 qdr sram data in 18 (vddq, gnd) / cmos input the qdr input data bus 18 b15 d19 qdr sram data in 19 (vddq, gnd) / cmos input the qdr input data bus 19 d20 d20 qdr sram data in 20 (vddq, gnd) / cmos input the qdr input data bus 20 d17 d21 qdr sram data in 21 (vddq, gnd) / cmos input the qdr input data bus 21
149 of 172 march 19, 2007 ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. idt 80KSBR200 advanced datasheet* a15 d22 qdr sram data in 22 (vddq, gnd) / cmos input the qdr input data bus 22 b21 d23 qdr sram data in 23 (vddq, gnd) / cmos input the qdr input data bus 23 b18 d24 qdr sram data in 24 (vddq, gnd) / cmos input the qdr input data bus 24 d16 d25 qdr sram data in 25 (vddq, gnd) / cmos input the qdr input data bus 25 b20 d26 qdr sram data in 26 (vddq, gnd) / cmos input the qdr input data bus 26 a19 d27 qdr sram data in 27 (vddq, gnd) / cmos input the qdr input data bus 27 e16 d28 qdr sram data in 28 (vddq, gnd) / cmos input the qdr input data bus 28 d19 d29 qdr sram data in 29 (vddq, gnd) / cmos input the qdr input data bus 29 d18 d30 qdr sram data in 30 (vddq, gnd) / cmos input the qdr input data bus 30 e17 d31 qdr sram data in 31 (vddq, gnd) / cmos input the qdr input data bus 31 c19 d32 qdr sram data in 32 (vddq, gnd) / cmos input the qdr input data bus 32 b19 d33 qdr sram data in 33 (vddq, gnd) / cmos input the qdr input data bus 33 e18 d34 qdr sram data in 34 (vddq, gnd) / cmos input the qdr input data bus 34 a20 d35 qdr sram data in 35 (vddq, gnd) / cmos input the qdr input data bus 35 a1 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. a8 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. a9 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. a10 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. a22 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. b2 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. b8 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. b9 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane.
150 of 172 march 19, 2007 ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. idt 80KSBR200 advanced datasheet* c1 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. c3 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. c18 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. d1 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. d3 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. d10 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. d12 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. e7 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. e9 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. e11 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. e13 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. f6 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. f8 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. f10 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. f12 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. f14 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. f16 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. f19 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. f21 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. g7 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. g9 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. g11 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane.
151 of 172 march 19, 2007 ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. idt 80KSBR200 advanced datasheet* g13 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. g15 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. g17 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. h6 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. h8 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. h10 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. h12 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. h14 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. h16 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. h20 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. j7 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. j9 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. j11 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. j13 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. j15 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. j17 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. k6 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. k8 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. k10 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. k12 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. k14 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. k16 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane.
152 of 172 march 19, 2007 ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. idt 80KSBR200 advanced datasheet* k20 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. l7 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. l9 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. l11 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. l13 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. l15 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. l17 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. m6 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. m8 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. m10 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. m12 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. m14 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. m16 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. m20 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. n7 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. n9 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. n11 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. n13 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. n15 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. n17 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. p6 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. p8 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane.
153 of 172 march 19, 2007 ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. idt 80KSBR200 advanced datasheet* p10 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. p12 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. p14 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. p16 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. p20 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. r7 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. r9 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. r11 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. r13 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. r15 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. r17 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. t6 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. t8 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. t10 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. t12 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. t14 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. t16 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. t20 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. u5 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. u7 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. u9 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. u11 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane.
154 of 172 march 19, 2007 ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. idt 80KSBR200 advanced datasheet* u13 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. u15 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. u17 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. v20 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. w1 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. y19 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. ab1 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. ab2 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. ab16 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. ab22 gnd digital ground (cmos) digital gnd. all pins must be tied to single potential ground plane. g1 gnda analog ground (cmos) analog gnd. all pins must be tied to single potential ground plane. g3 gnda analog ground (cmos) analog gnd. all pins must be tied to single potential ground plane. h2 gnda analog ground (cmos) analog gnd. all pins must be tied to single potential ground plane. m2 gnda analog ground (cmos) analog gnd. all pins must be tied to single potential ground plane. n1 gnda analog ground (cmos) analog gnd. all pins must be tied to single potential ground plane. n3 gnda analog ground (cmos) analog gnd. all pins must be tied to single potential ground plane. y7 gnda analog ground (cmos) analog gnd. all pins must be tied to single potential ground plane. y13 gnda analog ground (cmos) analog gnd. all pins must be tied to single potential ground plane. aa8 gnda analog ground (cmos) analog gnd. all pins must be tied to single potential ground plane. aa12 gnda analog ground (cmos) analog gnd. all pins must be tied to single potential ground plane. ab7 gnda analog ground (cmos) analog gnd. all pins must be tied to single potential ground plane. ab13 gnda analog ground (cmos) analog gnd. all pins must be tied to single potential ground plane.
155 of 172 march 19, 2007 ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. idt 80KSBR200 advanced datasheet* c7 gnds serdes ground (cmos) analog gnd for tx/rx pairs. all pins must be tied to single potential ground plane. c9 gnds serdes ground (cmos) analog gnd for tx/rx pairs. all pins must be tied to single potential ground plane. d5 gnds serdes ground (cmos) analog gnd for tx/rx pairs. all pins must be tied to single potential ground plane. e2 gnds serdes ground (cmos) analog gnd for tx/rx pairs. all pins must be tied to single potential ground plane. e4 gnds serdes ground (cmos) analog gnd for tx/rx pairs. all pins must be tied to single potential ground plane. f5 gnds serdes ground (cmos) analog gnd for tx/rx pairs. all pins must be tied to single potential ground plane. h4 gnds serdes ground (cmos) analog gnd for tx/rx pairs. all pins must be tied to single potential ground plane. h5 gnds serdes ground (cmos) analog gnd for tx/rx pairs. all pins must be tied to single potential ground plane. k2 gnds serdes ground (cmos) analog gnd for tx/rx pairs. all pins must be tied to single potential ground plane. k4 gnds serdes ground (cmos) analog gnd for tx/rx pairs. all pins must be tied to single potential ground plane. k5 gnds serdes ground (cmos) analog gnd for tx/rx pairs. all pins must be tied to single potential ground plane. m4 gnds serdes ground (cmos) analog gnd for tx/rx pairs. all pins must be tied to single potential ground plane. m5 gnds serdes ground (cmos) analog gnd for tx/rx pairs. all pins must be tied to single potential ground plane. p5 gnds serdes ground (cmos) analog gnd for tx/rx pairs. all pins must be tied to single potential ground plane. r2 gnds serdes ground (cmos) analog gnd for tx/rx pairs. all pins must be tied to single potential ground plane. r4 gnds serdes ground (cmos) analog gnd for tx/rx pairs. all pins must be tied to single potential ground plane.
156 of 172 march 19, 2007 ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. idt 80KSBR200 advanced datasheet* t1 gnds serdes ground (cmos) analog gnd for tx/rx pairs. all pins must be tied to single potential ground plane. t3 gnds serdes ground (cmos) analog gnd for tx/rx pairs. all pins must be tied to single potential ground plane. t5 gnds serdes ground (cmos) analog gnd for tx/rx pairs. all pins must be tied to single potential ground plane. v2 gnds serdes ground (cmos) analog gnd for tx/rx pairs. all pins must be tied to single potential ground plane. v4 gnds serdes ground (cmos) analog gnd for tx/rx pairs. all pins must be tied to single potential ground plane. v6 gnds serdes ground (cmos) analog gnd for tx/rx pairs. all pins must be tied to single potential ground plane. v8 gnds serdes ground (cmos) analog gnd for tx/rx pairs. all pins must be tied to single potential ground plane. v10 gnds serdes ground (cmos) analog gnd for tx/rx pairs. all pins must be tied to single potential ground plane. v12 gnds serdes ground (cmos) analog gnd for tx/rx pairs. all pins must be tied to single potential ground plane. v14 gnds serdes ground (cmos) analog gnd for tx/rx pairs. all pins must be tied to single potential ground plane. v16 gnds serdes ground (cmos) analog gnd for tx/rx pairs. all pins must be tied to single potential ground plane. w2 gnds serdes ground (cmos) analog gnd for tx/rx pairs. all pins must be tied to single potential ground plane. w5 gnds serdes ground (cmos) analog gnd for tx/rx pairs. all pins must be tied to single potential ground plane. w8 gnds serdes ground (cmos) analog gnd for tx/rx pairs. all pins must be tied to single potential ground plane. w10 gnds serdes ground (cmos) analog gnd for tx/rx pairs. all pins must be tied to single potential ground plane. w12 gnds serdes ground (cmos) analog gnd for tx/rx pairs. all pins must be tied to single potential ground plane.
157 of 172 march 19, 2007 ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. idt 80KSBR200 advanced datasheet* w15 gnds serdes ground (cmos) analog gnd for tx/rx pairs. all pins must be tied to single potential ground plane. y4 gnds serdes ground (cmos) analog gnd for tx/rx pairs. all pins must be tied to single potential ground plane. y16 gnds serdes ground (cmos) analog gnd for tx/rx pairs. all pins must be tied to single potential ground plane. aa5 gnds serdes ground (cmos) analog gnd for tx/rx pairs. all pins must be tied to single potential ground plane. aa10 gnds serdes ground (cmos) analog gnd for tx/rx pairs. all pins must be tied to single potential ground plane. aa15 gnds serdes ground (cmos) analog gnd for tx/rx pairs. all pins must be tied to single potential ground plane. ab4 gnds serdes ground (cmos) analog gnd for tx/rx pairs. all pins must be tied to single potential ground plane. a6 id0 i 2 c (vdd, gnd) / cmos input i 2 c slave id address bit 0. this should be set statically to vdd or gnd at power-up. note: supply / levels requirements are unque from the other i 2 c pins. b6 id1 i 2 c (vdd, gnd) / cmos input i 2 c slave id address bit 1. this should be set statically to vdd or gnd at power-up. a7 id2 i 2 c (vdd, gnd) / cmos input i 2 c slave id address bit 2. this should be set statically to vdd or gnd at power-up. b7 id3 i 2 c (vdd, gnd) / cmos input i 2 c slave id address bit 3. this should be set statically to vdd or gnd at power-up. d6 id4 i 2 c (vdd, gnd) / cmos input i 2 c slave id address bit 4. this should be set statically to vdd or gnd at power-up. c8 id5 i 2 c (vdd, gnd) / cmos input i 2 c slave id address bit 5. this should be set statically to vdd or gnd at power-up. d8 id6 i 2 c (vdd, gnd) / cmos input i 2 c slave id address bit 6. this should be set statically to vdd or gnd at power-up. c10 id7 i 2 c (vdd, gnd) / cmos input i 2 c slave id address bit 8. this should be set statically to vdd or gnd at power-up. c11 id8 i 2 c (vdd, gnd) / cmos input i 2 c slave id address bit 7. this should be set statically to vdd or gnd at power-up. c12 id9 i 2 c (vdd, gnd) / cmos input i 2 c slave id address bit 9. this should be set statically to vdd or gnd at power-up. u2 ids id select (vdd, gnd) / cmos input srio 8/16 bit destination id select aa1 irq0 interrupt 0 (vdd3, gnd) / cmos output this is an interrupt output pin whose value is given by the error management block.
158 of 172 march 19, 2007 ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. idt 80KSBR200 advanced datasheet* y1 irq1 interrupt 1 (vdd3, gnd) / cmos output this is an interrupt output pin whose value is given by the error management block. a11 mbdone memory bist (vdd, gnd) / cmos output mbist done. set (mbdone = 1) when mbist patterns are com- pleted b11 mbpass memory bist (vdd, gnd) / cmos output mbist pass. set (mbpass = 1) when mbist patterns pass. cleared (mbpass = 0) and is sticky when mbist fails. b3 mrst_n master reset (vdd, gnd) / cmos input serb global reset. sets all internal registers to default values. resets all plls. resets all port configurations. this is a hard reset. y17 pll_off pll off (vdd, gnd) / cmos input used for device testing with pll bypass. b10 ppe_n parallel port enable (vdd, gnd) / cmos input ppe = 0, p-port is active ppe = 1, p-port is powered down and not used (low power). p18 q0 qdr sram data out 0 (vddq, gnd) / cmos output the qdr output data bus 0 r18 q1 qdr sram data out 1 (vddq, gnd) / cmos output the qdr output data bus 1 p19 q2 qdr sram data out 2 (vddq, gnd) / cmos output the qdr output data bus 2 r19 q3 qdr sram data out 3 (vddq, gnd) / cmos output the qdr output data bus 3 t21 q4 qdr sram data out 4 (vddq, gnd) / cmos output the qdr output data bus 4 u21 q5 qdr sram data out 5 (vddq, gnd) / cmos output the qdr output data bus 5 t22 q6 qdr sram data out 6 (vddq, gnd) / cmos output the qdr output data bus 6 u22 q7 qdr sram data out 7 (vddq, gnd) / cmos output the qdr output data bus 7 n19 q8 qdr sram data out 8 (vddq, gnd) / cmos output the qdr output data bus 8 n18 q9 qdr sram data out 9 (vddq, gnd) / cmos output the qdr output data bus 9 r22 q10 qdr sram data out 10 (vddq, gnd) / cmos output the qdr output data bus 10 r21 q11 qdr sram data out 11 (vddq, gnd) / cmos output the qdr output data bus 11 p22 q12 qdr sram data out 12 (vddq, gnd) / cmos output the qdr output data bus 12 p21 q13 qdr sram data out 13 (vddq, gnd) / cmos output the qdr output data bus 13 n22 q14 qdr sram data out 14 (vddq, gnd) / cmos output the qdr output data bus 14 n21 q15 qdr sram data out 15 (vddq, gnd) / cmos output the qdr output data bus 15
159 of 172 march 19, 2007 ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. idt 80KSBR200 advanced datasheet* m22 q16 qdr sram data out 16 (vddq, gnd) / cmos output the qdr output data bus 16 m21 q17 qdr sram data out 17 (vddq, gnd) / cmos output the qdr output data bus 17 l21 q18 qdr sram data out 18 (vddq, gnd) / cmos output the qdr output data bus 18 l22 q19 qdr sram data out 19 (vddq, gnd) / cmos output the qdr output data bus 19 k21 q20 qdr sram- data out 20 (vddq, gnd) / cmos output the qdr output data bus 20 k22 q21 qdr sram data out 21 (vddq, gnd) / cmos output the qdr output data bus 21 j21 q22 qdr sram data out 22 (vddq, gnd) / cmos output the qdr output data bus 22 j22 q23 qdr sram data out 23 (vddq, gnd) / cmos output the qdr output data bus 23 l18 q24 qdrsram data out 24 (vddq, gnd) / cmos output the qdr output data bus 24 l19 q25 qdr sram data out 25 (vddq, gnd) / cmos output the qdr output data bus 25 h21 q26 qdr sram data out 26 (vddq, gnd) / cmos output the qdr output data bus 26 h22 q27 qdr sram data out 27 (vddq, gnd) / cmos output the qdr output data bus 27 g21 q28 qdr sram data out 28 (vddq, gnd) / cmos output the qdr output data bus 28 g22 q29 qdr sram data out 29 (vddq, gnd) / cmos output the qdr output data bus 29 k18 q30 qdr sram data out 30 (vddq, gnd) / cmos output the qdr output data bus 30 k19 q31 qdr sram data out 31 (vddq, gnd) / cmos output the qdr output data bus 31 h19 q32 qdr sram data out 32 (vddq, gnd) / cmos output the qdr output data bus 32 j19 q33 qdr sram data out 33 (vddq, gnd) / cmos output the qdr output data bus 33 j18 q34 qdr sram data out 34 (vddq, gnd) / cmos output the qdr output data bus 34 g19 q35 qdr sram data out 35 (vddq, gnd) / cmos output the qdr output data bus 35 aa17 qdra qdr mem size (vdd, gnd) / cmos input reserved and should be tied to ground. ab18 qdrb qdr mem size (vdd, gnd) / cmos input specifies what size qdr sram is connected externally. 0 = 16 address lines are active (36m qdr2 b4 sram) 1 = 17 address lines are active (72m qdr2 b4 sram)
160 of 172 march 19, 2007 ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. idt 80KSBR200 advanced datasheet* v21 rdo_n read strobe (vdd, gnd) / cmos output when qdr type sram attached, this output should be con- nected to the /rd input on the qdr sram(s). the fifo control- ler will use this pin to control the read function on the sram. ab3 refclkn serdes clock (vdd, gnd) / differential input negative side of differential input clock. this clock is used as the 156mhz reference for standard serdes operation. aa3 refclkp serdes clock (vdd, gnd) / differential input positive side of differential input clock. this clock is used as the 156mhz reference for standard serdes operation. v1 rextn rext external bias resistor. this pin must be connected to rextp with a 12k ohm resistor. this establishes the drive bias on the serdes output. this provides cml driver stability across process and temperature. u1 rextp rext external bias resistor. this pin must be connected to rextn with a 12k ohm resistor. l1 s1_rxn0 port 1 receive (vdds, gnds) / s-port 1 differential input negative end of differential receiver, s-port, lane 0 m1 s1_rxp0 port 1 receive (vdds, gnds) / s-port 1 differential input positive end of differential receiver, s-port, lane 0 l4 s1_rxn1 port 1 receive (vdds, gnds) / s-port 1 differential input negative end of differential receiver, s-port, lane 1 l3 s1_rxp1 port 1 receive (vdds, gnds) / s-port 1 differential input positive end of differential receiver, s-port, lane 1 j1 s1_rxn2 port 1 receive (vdds, gnds) / s-port 1 differential input negative end of differential receiver, s-port, lane 2 h1 s1_rxp2 port 1 receive (vdds, gnds) / s-port 1 differential input positive end of differential receiver, s-port, lane 2 j4 s1_rxn3 port 1 receive (vdds, gnds) / s-port 1 differential input negative end of differential receiver, s-port, lane 3 j3 s1_rxp3 port 1 receive (vdds, gnds) / s-port 1 differential input positive end of differential receiver, s-port, lane 3 p1 s1_txn0 port1 transmit (vdds, gnds) / s-port 1 differential output negative end of differential transmitter, s-port, lane 0 p2 s1_txp0 port1 transmit (vdds, gnds) / s-port 1 differential output positive end of differential transmitter, s-port, lane 0 p4 s1_txn1 port1 transmit (vdds, gnds) / s-port 1 differential output negative end of differential transmitter, s-port, lane 1 n4 s1_txp1 port1 transmit (vdds, gnds) / s-port 1 differential output positive end of differential transmitter, s-port, lane 1 f1 s1_txn2 port1 transmit (vdds, gnds) / s-port 1 differential output negative end of differential transmitter, s-port, lane 2 f2 s1_txp2 port1 transmit (vdds, gnds) / s-port 1 differential output positive end of differential transmitter, s-port, lane 2 f4 s1_txn3 port1 transmit (vdds, gnds) / s-port 1 differential output negative end of differential transmitter, s-port, lane 3 g4 s1_txp3 port1 transmit (vdds, gnds) / rio differential output positive end of differential transmitter, s-port, lane 3
161 of 172 march 19, 2007 ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. idt 80KSBR200 advanced datasheet* ab6 s2_rxn0 port 2 receive (vdds, gnds) negative end of differential receiver, s-port 2, lane 0 aa6 s2_rxp0 port 2 receive (vdds, gnds) positive end of differential receiver, s-port 2, lane 0 w6 s2_rxn1 port 2 receive (vdds, gnds) negative end of differential receiver, s-port 2, lane 1 w7 s2_rxp1 port 2 receive (vdds, gnds) positive end of differential receiver, s-port 2, lane 1 ab14 s2_rxn2 port 2 receive (vdds, gnds) negative end of differential receiver, s-port 2, lane 2 aa14 s2_rxp2 port 2 receive (vdds, gnds) positive end of differential receiver, s-port 2, lane 2 w14 s2_rxn3 port 2 receive (vdds, gnds) negative end of differential receiver, s-port 2, lane 3 w13 s2_rxp3 port 2 receive (vdds, gnds) positive end of differential receiver, s-port 2, lane 3 ab9 s2_txn0 port 2 transmit (vdds, gnds) negative end of differential transmitter, s-port 2, lane 0 ab8 s2_txp0 port 2 transmit (vdds, gnds) positive end of differential transmitter, s-port 2, lane 0 w9 s2_txn1 port 2 transmit (vdds, gnds) negative end of differential transmitter, s-port 2, lane 1 y9 s2_txp1 port 2 transmit (vdds, gnds) positive end of differential transmitter, s-port 2, lane 1 ab11 s2_txn2 port 2 transmit (vdds, gnds) negative end of differential transmitter, s-port 2, lane 2 ab12 s2_txp2 port 2 transmit (vdds, gnds) positive end of differential transmitter, s-port 2, lane 2 w11 s2_txn3 port 2 transmit (vdds, gnds) negative end of differential transmitter, s-port 2, lane 3 y11 s2_txp3 port 2 transmit (vdds, gnds) positive end of differential transmitter, s-port 2, lane 3 b12 scen scan (vdd, gnd) / cmos input scan enable. scan is enabled when scen = 1. scan clock is provided by sck while scen = 1. internal pull-down ensures dis- able if this pin is not driven. c4 scl i 2 c (vdd3, gnd) / cmos input i 2 c clock. this is also repurposed for the scan clock when scen = 1. c5 sda i 2 c (vdd3, gnd) / cmos io i 2 c serial data io. data direction is determined by the i 2 c read/ write bit. see i 2 c functionality for further detail. w3 sp1s0 s-port 1 speed select (vdd, gnd) / cmos input speed select pins. these pins define s-port port speed at reset for all ports. the reset setting may be overridden by subsequent programming of the quad_ctrl register. sp1s[1:0] = {00 = 1.25g, 01 = 2.5g, 10 = 3.125g, 11 = reserved}. these pins must remain statically biased after power-up. y3 sp1s1 s-port 1 speed select (vdd, gnd) / cmos input speed select pins. these pins define s-port port speed at reset for all ports. aa2 stoa serdes analog serdes analog test output. used for observing serdes out- puts. y2 stod serdes digital serdes digital test output. used for observing serdes out- puts. b4 tck jtag (vdd3, gnd) / cmos input jtag tap port clock b5 tdi jtag (vdd3, gnd) / cmos input jtag tap port input a5 tdo jtag (vdd3, gnd) / cmos output jtag tap port output
162 of 172 march 19, 2007 ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. idt 80KSBR200 advanced datasheet* a14 tm0 tmode0 (vdd3, gnd) / cmos input tm[2:0]; mbist enable for use in testing on-chip memories. mbist is enabled when mben = 1. internal pull-down ensures disable if this pin is not driven. b13 tm1 tmode1 (vdd3, gnd) / cmos input tm[2:0]; mbist enable for use in testing on-chip memories. a12 tm2 tmode2 (vdd3, gnd) / cmos input tm[2:0]; mbist enable for use in testing on-chip memories. a3 tms jtag (vdd3, gnd) / cmos input jtag tap port mode select a4 trst jtag (vdd3, gnd) / cmos input jtag tap port asynchronous reset c22 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. d2 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. d4 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. d11 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. d13 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. e6 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. e8 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. e10 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. e12 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. e14 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. e20 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. f7 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. f9 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. f11 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. f13 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. f17 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. g6 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. g8 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane.
163 of 172 march 19, 2007 ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. idt 80KSBR200 advanced datasheet* g10 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. g12 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. g14 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. h7 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. h9 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. h11 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. h13 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. j6 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. j8 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. j10 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. j12 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. j14 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. k7 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. k9 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. k11 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. k13 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. l6 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. l8 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. l10 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. l12 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. l14 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. m7 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane.
164 of 172 march 19, 2007 ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. idt 80KSBR200 advanced datasheet* m9 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. m11 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. m13 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. n6 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. n8 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. n10 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. n12 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. n14 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. p7 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. p9 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. p11 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. p13 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. r6 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. r8 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. r10 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. r12 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. r14 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. t7 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. t9 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. t11 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. t13 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. u4 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane.
165 of 172 march 19, 2007 ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. idt 80KSBR200 advanced datasheet* u6 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. u8 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. u10 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. u12 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. u14 vdd 1.2v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. a2 vdd3 2.5v / 3.3v jtag power (cmos) digital jtag pin vdd3. all pins must be tied to single potential power supply plane. b1 vdd3 2.5v / 3.3v jtag power (cmos) digital jtag pin vdd3. all pins must be tied to single potential power supply plane. c2 vdd3 2.5v / 3.3v jtag power (cmos) digital jtag pin vdd3. all pins must be tied to single potential power supply plane. f3 vdda analog power (cmos) analog vdd. all pins must be tied to single potential power sup- ply plane. g2 vdda analog power (cmos) analog vdd. all pins must be tied to single potential power sup- ply plane. h3 vdda analog power (cmos) analog vdd. all pins must be tied to single potential power sup- ply plane. m3 vdda analog power (cmos) analog vdd. all pins must be tied to single potential power sup- ply plane. n2 vdda analog power (cmos) analog vdd. all pins must be tied to single potential power sup- ply plane. p3 vdda analog power (cmos) analog vdd. all pins must be tied to single potential power sup- ply plane. y6 vdda analog power (cmos) analog vdd. all pins must be tied to single potential power sup- ply plane. y8 vdda analog power (cmos) analog vdd. all pins must be tied to single potential power sup- ply plane. y12 vdda analog power (cmos) analog vdd. all pins must be tied to single potential power sup- ply plane. y14 vdda analog power (cmos) analog vdd. all pins must be tied to single potential power sup- ply plane. aa7 vdda analog power (cmos) analog vdd. all pins must be tied to single potential power sup- ply plane. aa13 vdda analog power (cmos) analog vdd. all pins must be tied to single potential power sup- ply plane. a21 vddq 1.5v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane.
166 of 172 march 19, 2007 ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. idt 80KSBR200 advanced datasheet* c16 vddq 1.5v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. c20 vddq 1.5v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. f15 vddq 1.5v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. f18 vddq 1.5v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. f22 vddq 1.5v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. g16 vddq 1.5v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. g20 vddq 1.5v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. h15 vddq 1.5v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. h17 vddq 1.5v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. j16 vddq 1.5v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. j20 vddq 1.5v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. k15 vddq 1.5v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. k17 vddq 1.5v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. l16 vddq 1.5v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. l20 vddq 1.5v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. m15 vddq 1.5v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. m17 vddq 1.5v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. n16 vddq 1.5v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. n20 vddq 1.5v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. p15 vddq 1.5v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. p17 vddq 1.5v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. r16 vddq 1.5v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane.
167 of 172 march 19, 2007 ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. idt 80KSBR200 advanced datasheet* r20 vddq 1.5v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. t15 vddq 1.5v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. t17 vddq 1.5v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. u16 vddq 1.5v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. u20 vddq 1.5v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. w20 vddq 1.5v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. ab21 vddq 1.5v digital power (cmos) digital vdd. all pins must be tied to single potential power supply plane. d7 vdds serdes power (cmos) analog vdd for tx/rx pairs. all pins must be tied to single potential power supply plane. d9 vdds serdes power (cmos) analog vdd for tx/rx pairs. all pins must be tied to single potential power supply plane. e1 vdds serdes power (cmos) analog vdd for tx/rx pairs. all pins must be tied to single potential power supply plane. e3 vdds serdes power (cmos) analog vdd for tx/rx pairs. all pins must be tied to single potential power supply plane. e5 vdds serdes power (cmos) analog vdd for tx/rx pairs. all pins must be tied to single potential power supply plane. g5 vdds serdes power (cmos) analog vdd for tx/rx pairs. all pins must be tied to single potential power supply plane. j2 vdds serdes power (cmos) analog vdd for tx/rx pairs. all pins must be tied to single potential power supply plane. j5 vdds serdes power (cmos) analog vdd for tx/rx pairs. all pins must be tied to single potential power supply plane. k1 vdds serdes power (cmos) analog vdd for tx/rx pairs. all pins must be tied to single potential power supply plane. k3 vdds serdes power (cmos) analog vdd for tx/rx pairs. all pins must be tied to single potential power supply plane. l2 vdds serdes power (cmos) analog vdd for tx/rx pairs. all pins must be tied to single potential power supply plane. l5 vdds serdes power (cmos) analog vdd for tx/rx pairs. all pins must be tied to single potential power supply plane. n5 vdds serdes power (cmos) analog vdd for tx/rx pairs. all pins must be tied to single potential power supply plane. r1 vdds serdes power (cmos) analog vdd for tx/rx pairs. all pins must be tied to single potential power supply plane. r3 vdds serdes power (cmos) analog vdd for tx/rx pairs. all pins must be tied to single potential power supply plane.
168 of 172 march 19, 2007 ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. idt 80KSBR200 advanced datasheet* r5 vdds serdes power (cmos) analog vdd for tx/rx pairs. all pins must be tied to single potential power supply plane. t2 vdds serdes power (cmos) analog vdd for tx/rx pairs. all pins must be tied to single potential power supply plane. t4 vdds serdes power (cmos) analog vdd for tx/rx pairs. all pins must be tied to single potential power supply plane. v5 vdds serdes power (cmos) analog vdd for tx/rx pairs. all pins must be tied to single potential power supply plane. v7 vdds serdes power (cmos) analog vdd for tx/rx pairs. all pins must be tied to single potential power supply plane. v9 vdds serdes power (cmos) analog vdd for tx/rx pairs. all pins must be tied to single potential power supply plane. v11 vdds serdes power (cmos) analog vdd for tx/rx pairs. all pins must be tied to single potential power supply plane. v13 vdds serdes power (cmos) analog vdd for tx/rx pairs. all pins must be tied to single potential power supply plane. v15 vdds serdes power (cmos) analog vdd for tx/rx pairs. all pins must be tied to single potential power supply plane. w4 vdds serdes power (cmos) analog vdd for tx/rx pairs. all pins must be tied to single potential power supply plane. w16 vdds serdes power (cmos) analog vdd for tx/rx pairs. all pins must be tied to single potential power supply plane. y5 vdds serdes power (cmos) analog vdd for tx/rx pairs. all pins must be tied to single potential power supply plane. y10 vdds serdes power (cmos) analog vdd for tx/rx pairs. all pins must be tied to single potential power supply plane. y15 vdds serdes power (cmos) analog vdd for tx/rx pairs. all pins must be tied to single potential power supply plane. aa4 vdds serdes power (cmos) analog vdd for tx/rx pairs. all pins must be tied to single potential power supply plane. aa9 vdds serdes power (cmos) analog vdd for tx/rx pairs. all pins must be tied to single potential power supply plane. aa11 vdds serdes power (cmos) analog vdd for tx/rx pairs. all pins must be tied to single potential power supply plane. aa16 vdds serdes power (cmos) analog vdd for tx/rx pairs. all pins must be tied to single potential power supply plane. ab5 vdds serdes power (cmos) analog vdd for tx/rx pairs. all pins must be tied to single potential power supply plane. ab10 vdds serdes power (cmos) analog vdd for tx/rx pairs. all pins must be tied to single potential power supply plane. ab15 vdds serdes power (cmos) analog vdd for tx/rx pairs. all pins must be tied to single potential power supply plane. a13 vref reference volt- age (cmos) toggle point reference voltage for hstl inputs
169 of 172 march 19, 2007 ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. idt 80KSBR200 advanced datasheet* 17.0 package specifications 17.1 package physical & thermal specifications package: super flipchip fcbga(br484) dimensions: 23 x 23mm ball count: 484 ball diameter: 0.6mm ball pitch: 1.0mm theta j a = {11.9c/w @ 0m/s, 8 c/w @ 1m/s, 7.3 c/w @ 2m/s} theta j c = 0.2 c/w u19 wro_n write strobe (vdd, gnd) / cmos output when qdr type sram attached, this output should be con- nected to the /wr input on the qdr sram(s). the fifo control- ler will use this pin to control the write function on the sram. ab17 zq p-port impedance m18 dnc do not connect m19 dnc do not connect t18 dnc do not connect t19 dnc do not connect
170 of 172 march 19, 2007 ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. idt 80KSBR200 advanced datasheet* 17.2 package drawing figure 54 serb package drawing 1 of 2 www.idt.com t id
171 of 172 march 19, 2007 ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. idt 80KSBR200 advanced datasheet* figure 55 serb package drawing 2 of 2 www.idt.com t id
172 of 172 march 19, 2007 idt 80KSBR200 advanced datasheet* corporate headquarters 6024 silver creek valley road san jose, ca 95138 for sales: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com for tech support: 831-284-2794 dualporthelp@idt.com ?2005 integrated device technology, inc. all rights reserved. advanced datasheet for informational purposes only. product spec ifications subject to change without notice. not an offer for sale the information presented herein is subject to a non-disclosure agreement (nda) and is for planning purposes only. nothing contained in this presentation, whether verbal or wri tten, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. 18.0 references and standards [1] ?the i 2 c-bus specification?, version 2.1, january 2000, phillips [2] rapidio tm interconnect specification, part 1: input/output logical specification, rev. 1.3, 06/2005, rta [3] rapidio tm interconnect specification, part 2: message passing logical specification, rev. 1.3, 06/2005, rta [4] rapidio tm interconnect specification, part 3: common transport specification, rev. 1.3, 06/2005, rta [5] rapidio tm interconnect specification, part 6: 1x/4x lp-serial physical layer specification, rev. 1.3, 06/2005, rta [6] rapidio tm interconnect specification, part 7: system and device inter-operability specification, rev. 1.3, 06/2005, rta [7] rapidio tm interconnect specification, part 8: error management extensions specification, rev. 1.3, 06/2005, rta [8] rapidio tm interconnect specification, part 9: flow control logic lay er extensions specification, rev. 1.3, 06/2005, rta [9] rapidio tm interconnect specification, annex i: software/system bring up specification, rev. 1.3, 06/2005, rta [10] rapidio tm specification revision 1.2: errata 1, rev. 1, 06/2003, rapidio tm trade association [11] ieee std 1149.1-2001 ieee standard test access port and boundary-scan architecture [12] ieee std 1149.6-2003 ieee standard for boundary-scan testing of advanced digital networks [13] qdr2 sram, datasheet, samsung, k7r163684b [14] jedec standard, jesd8-6 hstl 19.0 revision history 10/06/06: initial advanced datasheet (rev a) 03/01/07: advanced datasheet (rev b) 19.1 advanced datasheet: (definition) ?advanced datasheet contain descriptions for products that are in early release. ?advanced datasheets are informational only. a dvanced specifi- cations are subject to change without notice. 20.0 ordering information for specific speeds, packages and powers, contact your sales office

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